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AD7294

Data Sheet

Rev. I | Page 22 of 47

20kΩ

220kΩ

2 × VREF p-p

27Ω

V+

V–

V+

V–

GND

2.5V

3.75V

1.25V

2.5V

3.75V

1.25V

REFOUT ADC

VIN+

AD7294

VIN–

440Ω

220Ω

0.47µF

1ADDITIONAL PINS OMITTED FOR CLARITY.

220Ω

10kΩ

Figure 39. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal

into a Differential Unipolar Signal

Pseudo Differential Mode

The four uncommitted analog input channels can be configured

as two pseudo differential pairs. Uncommitted input, VIN0 and

VIN1, are a pseudo differential pair, as are VIN2 and VIN3. In this

mode, VIN+ is connected to the signal source, which can have a

maximum amplitude of VREF (or 2 × VREF, depending on the

range chosen) to make use of the full dynamic range of the

device. A dc input is applied to VIN−. The voltage applied to this

input provides an offset from ground or a pseudo ground for the

VIN+ input. Which channel is VIN+ is determined by the ADC

channel allocation. The differential mode must be selected to

operate in the pseudo differential mode. The resulting converted

pseudo differential data is stored in twos complement format in the

result register.

The governing equation for the pseudo differential mode, for

VIN0 is

VOUT = 2(VIN+ − VIN−) − VREF_ADC

where VIN+ is the single-ended signal and VIN− is a dc voltage.

The benefit of pseudo differential inputs is that they separate

the analog input signal ground from the ADC ground, allowing

dc common-mode voltages to be cancelled. The typical voltage

range for VIN− while in pseudo differential mode is shown in

Figure 40; Figure 41 shows a connection diagram for pseudo

differential mode.

2.0

1.5

1.0

0.5

–0.5

VREF (V)

AVDD = DVDD = 5V

VDRIVE = 5V

Figure 40. VIN− Input Range vs. VREF in Pseudo Differential Mode

DC INPUT

VOLTAGE

VREF

p-p

REFOUT/REFIN ADC

VIN+

AD7294

VIN–

0.47µF

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 41. Pseudo Differential Mode Connection Diagram

CURRENT SENSOR

Two bidirectional high-side current sense amplifiers are

provided that can accurately amplify differential current shunt

voltages in the presence of high common-mode voltages from

AVDD up to 59.4 V. Each amplifier can accept a ±200 mV

differential input. Both current sense amplifiers have a fixed

gain of 12.5 and utilize an internal 2.5 V reference.

An analog comparator is also provided with each amplifier for

fault detection. The threshold is defined as

1.2 × Full-Scale Voltage Range

When this limit is reached, the output is latched onto a

dedicated pin. This output remains high until the latch is

cleared by writing to the appropriate register.

AD7294

AVDD TO 54.5V

RS(+)

RSENSE

ILOAD

RS(–)

40kΩ

100kΩ

VOUT

TO MUX

VPP

Figure 42. High-Side Current Sense

The AD7294 current sense comprises two main blocks: a

differential and an instrumentation amplifier. A load current

flowing through the external shunt resistor produces a voltage

at the input terminals of the AD7294. Resistors R1 and R2

connect the input terminals to the differential amplifier (A1).

A1 nulls the voltage appearing across its own input terminals

by adjusting the current through R1 and R2 with Transistor Q1

and Transistor Q2. Common-mode feedback maintains the sum

of these currents at approximately 50 μA. When the input signal

to the AD7294 is zero, the currents in R1 and R2 are equal. When

the differential signal is nonzero, the current increases through

one of the resistors and decreases in the other. The current differ-

ence is proportional to the size and polarity of the input signal.

The differential currents through Q1 and Q2 are converted into

a differential voltage by R3 and R4. A2 is configured as an instru-

mentation amplifier, buffering this voltage and providing additional

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