S29WS064N0LBAI011 datasheet(49/99 Pages) SPANSION

49 / 99 page

January 25, 2005 S29WS-N_00_G0

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Information

7.6

Simultaneous Read/Write

The simultaneous read/write feature allows the host system to read data from one bank of mem-

ory while programming or erasing another bank of memory. An erase operation may also be

suspended to read from or program another location within the same bank (except the sector

being erased). Figure 11.24, Back-to-Back Read/Write Cycle Timings, shows how read and write

cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Character-

istics (CMOS Compatible) table for read-while-program and read-while-erase current

specification.

7.7

Writing Commands/Command Sequences

When the device is configured for Asynchronous read, only Asynchronous write operations are

allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device is able

to perform both Asynchronous and Synchronous write operations. CLK and AVD# induced address

latches are supported in the Synchronous programming mode. During a synchronous write oper-

ation, to write a command or command sequence (which includes programming data to the

device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE#

to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH

when writing commands or data. During an asynchronous write operation, the system must drive

CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses

are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of

WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device.

Tables 6.1–6.3 indicate the address space that each sector occupies. The device address space is

divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and

15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A “bank address” is the

set of address bits required to uniquely select a bank. Similarly, a “sector address” is the address

bits required to uniquely select a sector. ICC2 in “DC Characteristics” represents the active current

specification for the write mode. “AC Characteristics-Synchronous” and “AC Characteristics-Asyn-

chronous” contain timing specification tables and timing diagrams for write operations.

7.8

Handshaking

The handshaking feature allows the host system to detect when data is ready to be read by simply

monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.

When the device is configured to operate in synchronous mode, and OE# is low (active), the initial

word of burst data becomes available after either the falling or rising edge of the RDY pin (de-

pending on the setting for bit 10 in the Configuration Register). It is recommended that the host

system set CR13–CR11 in the Configuration Register to the appropriate number of wait states to

ensure optimal burst mode operation (see Table 7.8, Configuration Register).

Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same

time that data is ready, or one cycle before data is ready.

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