S29WS064N0LBAI011 datasheet(91/99 Pages) SPANSION

91 / 99 page

January 25, 2005 S29WS-N_00_G0

Ad vance

Information

Table 12.2. Sector Protection Commands

Command Sequence

(Notes)

Bus Cycles (Notes 1–4)

First

Second

Third

Fourth

Fifth

Sixth

Seventh

Addr

Data

Addr

Data

Addr

Data

Addr

Data Addr Data Addr Data Addr Data

Lock

Bits

Command Set Entry (5)

555

2AA

555

Program (6, 12)

77/00

data

Read (6)

data

Command Set Exit (7)

Password

Protection

Command Set Entry (5)

555

2AA

555

Program [0-3] (8)

PWD[0-3]

Read (9)

4 0...00 PWD0 0...01

PWD1

0...02

PWD2 0...03 PWD3

Unlock

PWD0

PWD1

PWD2

PWD3

Command Set Exit (7)

Non-Volatile

Sector

Protection (PPB)

Command Set Entry (5)

555

2AA

[BA]555

PPB Program (10)

All PPB Erase (10, 11)

PPB Status Read

RD(0)

Command Set Exit (7)

Global

Volatile Sector

Protection

Freeze

(PPB Lock)

Command Set Entry (5)

555

2AA

[BA]555

PPB Lock Bit Set

PPB Lock Bit Status Read

RD(0)

Command Set Exit (7)

Volatile Sector

Protection

(DYB)

Command Set Entry (5)

555

2AA

[BA]555

DYB Set

DYB Clear

DYB Status Read

RD(0)

Command Set Exit (7)

Legend:

X = Don’t care.

RA = Address of the memory location to be read.

PD(0) = SecSi Sector Lock Bit. PD(0), or bit[0].

PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must

be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.

PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must

be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.

PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].

SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;

WS064N = A21–A14.

BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;

WS064N = A21–A18.

PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit

combinations that represent the 64-bit Password

PWA = Password Address. Address bits A1 and A0 are used to select

each 16-bit portion of the 64-bit entity.

PWD = Password Data.

RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If

protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,

DQ2 = 1.

Notes:

1. All values are in hexadecimal.

2. Shaded cells indicate read cycles.

3. Address and data bits not specified in table, legend, or notes are

don’t cares (each hex digit implies 4 bits of data).

4. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state.

The system must write the reset command to return the device

to reading array data.

5. Entry commands are required to enter a specific mode to enable

instructions only available within that mode.

6. If both the Persistent Protection Mode Locking Bit and the

Password Protection Mode Locking Bit are set at the same time,

the command operation aborts and returns the device to the

default Persistent Sector Protection Mode during 2nd bus cycle.

Note that on all future devices, addresses equal 00h, but is

currently 77h for the WS256N only. See Tables 8.1 and 8.2 for

explanation of lock bits.

7. Exit command must be issued to reset the device into read

mode; device may otherwise be placed in an unknown state.

8. Entire two bus-cycle sequence must be entered for each portion

of the password.

9. Full address range is required for reading password.

10. See Figure 8.2 for details.

11. “All PPB Erase” command pre-programs all PPBs before erasure

to prevent over-erasure.

12. The second cycle address for the lock register program operation

is 77 for S29Ws256N; however, for WS128N and Ws064N this

address is 00.

S29WS064N0LBAI011 Datasheet(PDF) 91 Page - SPANSION

S29WS064N0LBAI011 Datasheet(HTML) 91 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

Datasheet Download

Link URL