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S29WS064N0LBAI011 Datasheet(PDF) 80 Page - SPANSION |
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S29WS064N0LBAI011 Datasheet(HTML) 80 Page - SPANSION |
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80 / 99 page ![]() 78 S29WS-N_00_G0 January 25, 2005 Adva nce Information Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during command sequence unlock cycles. 4. Addresses are latched on the first rising edge of CLK. 5. Either CE# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the Synchronous Read Mode. Figure 11.15. Synchronous Program Operation Timings OE# CE# Data Addresses WE# CLK VCC 555h PD tWC tWPH tWP PA tVCS tDH tCH In Progress tWHWH1 VA Complete VA Program Command Sequence (last two cycles) Read Status Data tDS tAVDP A0h tAS tCAS tAH tAVCH tCSW tAVSC AVD# |
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