S29WS064N0LBAI011 datasheet(90/99 Pages) SPANSION

90 / 99 page

S29WS-N_00_G0 January 25, 2005

Adva nce

Information

Table 12.1.

Memory Array Commands

Command Sequence

(Notes)

Bus Cycles (Notes 1–5)

First

Second

Third

Fourth

Fifth

Sixth

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Asynchronous Read (6)

Reset (7)

XXX

Manufacturer ID

555

2AA

[BA]555

[BA]X00

0001

Device ID (9)

555

2AA

[BA]555

[BA]X01

227E

BA+X0E

Data

BA+X0F 2200

Indicator Bits (10)

555

2AA

[BA]555

[BA]X03

Data

Program

555

2AA

555

Write to Buffer (11)

555

2AA

WBL

Program Buffer to Flash

Write to Buffer Abort Reset (12)

555

2AA

555

Chip Erase

555

2AA

555

2AA

555

Sector Erase

555

2AA

555

2AA

Erase/Program Suspend (13)

Erase/Program Resume (14)

Set Configuration Register (18)

555

2AA

555

X00

Read Configuration Register

555

2AA

555

X00

CFI Query (15)

[BA]555

Entry

555

2AA

555

Program (16)

XXX

CFI (16)

XXX

Reset

XXX

Entry

555

2AA

555

Program (17)

555

2AA

555

Read (17)

Data

Exit (17)

555

2AA

555

XXX

Legend:

X = Don’t care.

RA = Read Address.

RD = Read Data.

PA = Program Address. Addresses latch on the rising edge of the

AVD# pulse or active edge of CLK, whichever occurs first.

PD = Program Data. Data latches on the rising edge of WE# or CE#

pulse, whichever occurs first.

SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;

WS064N = A21–A14.

BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;

WS064N = A21–A18.

CR = Configuration Register data bits D15–D0.

WBL = Write Buffer Location. Address must be within the same write

buffer page as PA.

WC = Word Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 7.1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells indicate read cycles.

4. Address and data bits not specified in table, legend, or notes are

don’t cares (each hex digit implies 4 bits of data).

5. Writing incorrect address and data values or writing them in the

improper sequence may place the device in an unknown state.

The system must write the reset command to return the device

to reading array data.

6. No unlock or command cycles required when bank is reading

array data.

7. Reset command is required to return to reading array data (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high

(while the bank is providing status information) or performing

sector lock/unlock.

8. The system must provide the bank address. See Autoselect

section for more information.

9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231

(WS128N).

10. See Table 7.9 for indicator bit values.

11. Total number of cycles in the command sequence is determined

by the number of words written to the write buffer.

12. Command sequence resets device for next command after write-

to-buffer operation.

13. System may read and program in non-erasing sectors, or enter

the autoselect mode, when in the Erase Suspend mode. The

Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

14. Erase Resume command is valid only during the Erase Suspend

mode, and requires the bank address.

15. Command is valid when device is ready to read array data or

when device is in autoselect mode. Address equals 55h on all

future devices, but 555h for WS256N/128N/064N.

16. Requires Entry command sequence prior to execution. Unlock

Bypass Reset command is required to return to reading array

data.

17. Requires Entry command sequence prior to execution. SecSi

Sector Exit Reset command is required to exit this mode; device

may otherwise be placed in an unknown state.

18. Requires reset command to configure the Configuration Register.

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