CS5530A datasheet(205/259 Pages) NSC

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Display Configuration Register (R/W)

Reset Value = 00000000h

DDC Input Data (Read Only): This is the DDC input data bit for reads.

30:28

Reserved: Set to 0.

Flat Panel On (Read Only): This bit indicates whether the attached flat panel display is powered on or off. The bit transi-

tions at the end of the power-up or power-down sequence. 0 = Off; 1 = On.

Reserved: Set to 0.

16-Bit Graphics Enable: This bit works in conjunction with the 16-bit Video Interface bit at F4BAR+Memory Offset 00h[29].

This bit should be set to the same value as the 16-bit Video Interface bit.

DDC Output Enable: This bit enables the DDC_SDA line to be driven for write data. 0 = DDC_SDA (pin M4) is an input;

1 = DDC_SDA (pin M4) is an output.

DDC Output Data: This is the DDC data bit.

DDC Clock: This is the DDC clock bit. It is used to clock the DDC_SDA bit.

Palette Bypass: Selects whether graphics or video data should bypass the gamma RAM.

0 = Video data; 1 = Graphics data.

Video/Graphics Color Key Select: Selects whether the video or graphics data stream will be used for color/chroma keying.

0 = Graphics data is compared to color key; 1 = Video data is compared to color key.

19:17

Power Sequence Delay: This field selects the number of frame periods that transpire between successive transitions of the

power sequence control lines. Valid values are 001 to 111.

16:14

CRT Sync Skew: This 3-bit field represents the number of pixel clocks to skew the horizontal and vertical syncs that are

sent to the CRT. This field should be programmed to 100 as the baseline. The syncs may be moved forward or backward rel-

ative to the pixel data via this register. It is used to compensate for the pipeline delay through the graphics pipeline.

Flat Panel Dither Enable: This bit enables flat panel dithering. It enables 24 bpp display data to be approximated with an

18-bit flat panel display. 0 = Disable; 1 = Enable.

XGA Flat Panel: This bit enables the FP_CLK_ EVEN output signal which can be used to demultiplex the FP_DATA bus into

even and odd pixels. 0 = Standard flat panel; 1 = XGA flat panel.

Flat Panel Vertical Synchronization Polarity: Selects the flat panel vertical sync polarity.

0 = FP vertical sync is normally low, transitioning high during sync interval.

1 = FP vertical sync is normally high, transitioning low during sync interval.

Flat Panel Horizontal Synchronization Polarity: Selects the flat panel horizontal sync polarity.

0 = FP horizontal sync is normally low, transitioning high during sync interval.

1 = FP horizontal sync is normally high, transitioning low during sync interval.

CRT Vertical Synchronization Polarity: Selects the CRT vertical sync polarity.

0 = CRT vertical sync is normally low, transitioning high during sync interval.

1 = CRT vertical sync is normally high, transitioning low during sync interval.

CRT Horizontal Synchronization Polarity: Selects the CRT horizontal sync polarity.

0 = CRT horizontal sync is normally low, transitioning high during sync interval.

1 = CRT horizontal sync is normally high, transitioning low during sync interval.

Flat Panel Data Enable: Enables the flat panel data bus.

0 = FP_DATA [17:0] is forced low;

1 = FP_DATA [17:0] is driven based upon power sequence control.

Flat Panel Power Enable: The transition of this bit initiates a flat panel power-up or power-down sequence.

0 -> 1 = Power-up flat panel;

1 -> 0 = Power-down flat panel.

DAC Power-Down (active low): This bit must be set to power-up the video DACs. It can be cleared to power-down the

video DACs when not in use. 0 = DACs are powered down; 1 = DACs are powered up.

Reserved: Set to 0.

DAC Blank Enable: This bit enables the blank to the video DACs.

0 = DACs are constantly blanked; 1 = DACs are blanked normally.

CRT Vertical Sync Enable: Enables the CRT vertical sync. Used for VESA DPMS support. 0 = Disable; 1 = Enable.

CRT Horizontal Sync Enable: Enables the CRT horizontal sync. Used for VESA DPMS support.

0 = Disable; 1 = Enable.

Display Enable: Enables the graphics display pipeline. It is used as a reset for the display control logic.

0 = Reset display control logic; 1 = Enable display control logic.

Table 4-23. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 205 Page - National Semiconductor (TI)

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