CS5530A datasheet(208/259 Pages) NSC

208 / 259 page

www.national.com

208

Revision 1.1

Offset 28h-2Bh

CRC Signature and TFT/TV Configuration Register (R/W)

Reset Value = 00000100h

31:8

24-Bit Video Signature Data (Read Only)

SYNC Override: Drive VSYNC_OUT on FP_VSYNC_OUT and HSYNC_OUT on FP_HSYNC_OUT.

0 = Disable; 1 = Enable.

Invert FP_CLK: 0 = Disable; 1 = Enable. (Applicable for TV not TFT.)

Invert FP_CLK_EVEN: 0 = Disable; 1 = Enable.

Reserved (Read Only)

Signature Source Select: 0 = RGB data; 1 = FP data. (FP data occupies the top 6 bits of each color byte to the signature,

with the bottom two bits always zero.)

Signature Free Run: 0 = Disable; 1 = Enable.

When high, with the signature enabled, the signature generator captures data continuously across multiple frames. This bit

may be set high when the signature is started, then later set low, which causes the signature generation process to stop at

the end of the current frame.

FP_HSYNC_OUT Delay: 0 = Disable; 1 = Enable. (Applicable for TFT not TV.)

When SYNC Override (bit 7) is high, this bit (bit 1) can be set high to delay FP_HSYNC_OUT by an extra two clock cycles.

When the SYNC Override (bit 7) is low, this bit should also be set low.

Signature Enable: 0 = Disable; 1= Enable.

When low, the signature register is reset to 000001h and held (no capture). When high, the signature register captures the

pixel data signature with each pixel clock beginning with the next vsync.

Offset 2Ch-FFh

Reserved

Reset Value = xxh

Table 4-23. F4BAR+Memory Offset xxh: Video Controller Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 208 Page - National Semiconductor (TI)