CS5530A datasheet(212/259 Pages) NSC

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Revision 1.1

Index 3Eh

Min. Grant Register (RO)

Reset Value = 00h

This register specifies the desired settings for how long of a burst the USB needs assuming a clock rate of 33 MHz. The value specifies

a period of time in units of 1/4 microsecond.

Index 3Fh

Max. Latency Register (RO)

Reset Value = 50h

This register specifies the desired settings for how often the USB needs access to the PCI bus assuming a clock rate of 33 MHz. The

value specifies a period of time in units of 1/4 microsecond.

Index 40h-43h

ASIC Test Mode Enable Register (R/W)

Reset Value = 000F0000h

Used for internal debug and test purposes only.

Index 44h-45h

ASIC Operational Mode Enable Register (R/W)

Reset Value = 0000h

15:9

Reserved: Read/Write 0s.

SIE Pipeline Disable: When set, waits for all USB bus activity to complete prior to returning completion status to the List

Processor. This is a fail-safe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12

MHz.

7:1

Write Only: Read as 0s.

Data Buffer Region 16: When set, the size of the region for the data buffer is 16 bytes. Otherwise, the size is 32 bytes.

Index 46h-47h

Reserved

Reset Value = 00h

Index 48h-FFh

Reserved

Reset Value = xxh

Table 4-25. USB Index xxh: USB PCI Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 212 Page - National Semiconductor (TI)