CS5530A datasheet(213/259 Pages) NSC

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Table 4-26. USB BAR+Memory Offset xxh: USB Controller Registers

Bit

Description

Offset 00h-03h

HcRevision Register (RO)

Reset Value = 00000110h

31:8

Reserved: Read/Write 0s.

7:0

Revision (Read Only): Indicates the Open HCI Specification revision number implemented by the Hardware. USB sup-

ports 1.0 specification. (X.Y = XYh).

Offset 04h-07h

HcControl Register (R/W)

Reset Value = 00000000h

31:11

Reserved: Read/Write 0s.

RemoteWakeupConnectedEnable: If a remote wakeup signal is supported, this bit enables that operation. Since there is

no remote wakeup signal supported, this bit is ignored.

RemoteWakeupConnected (Read Only): This bit indicated whether the HC supports a remote wakeup signal. This imple-

mentation does not support any such signal. The bit is hard-coded to 0.

InterruptRouting: This bit is used for interrupt routing: 0 = Interrupts routed to normal interrupt mechanism (INT);

1 = Interrupts routed to SMI.

7:6

HostControllerFunctionalState: This field sets the HC state. The HC may force a state change from UsbSuspend to

UsbResume after detecting resume signaling from a downstream port. States are:

00 = UsbReset

01 = UsbResume

10 = UsbOperational

11 = UsbSuspend

BulkListEnable: When set, this bit enables processing of the Bulk list.

ControlListEnable: When set, this bit enables processing of the Control list.

IsochronousEnable: When clear, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs

may be serviced). While processing the Periodic List, the HC will check this bit when it finds an isochronous ED.

PeriodicListEnable: When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The HC checks

this bit prior to attempting any periodic transfers in a frame.

1:0

ControlBulkServiceRatio: Specifies the number of Control Endpoints serviced for every Bulk Endpoint. Encoding is N-1

where N is the number of Control Endpoints (i.e., 00 = 1 Control Endpoint; 11 = 3 Control Endpoints).

Offset 08h-0Bh

HcCommandStatus Register (R/W)

Reset Value = 00000000h

31:18

Reserved: Read/Write 0s.

17:16

ScheduleOverrunCount: This field increments every time the SchedulingOverrun bit in HcInterruptStatus is set. The count

wraps from 11 to 00.

15:4

Reserved: Read/Write 0s.

OwnershipChangeRequest: When set by software, this bit sets the OwnershipChange field in HcInterruptStatus. The bit is

cleared by software.

BulkListFilled: Set to indicate there is an active ED on the Bulk List. The bit may be set by either software or the HC and

cleared by the HC each time it begins processing the head of the Bulk List.

ControlListFilled: Set to indicate there is an active ED on the Control List. It may be set by either software or the HC and

cleared by the HC each time it begins processing the head of the Control List.

HostControllerReset: This bit is set to initiate a software reset. This bit is cleared by the HC upon completion of the reset

operation.

Offset 0Ch-0Fh

HcInterruptStatus Register (R/W)

Reset Value = 00000000h

Reserved: Read/Write 0s.

OwnershipChange: This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set.

29:7

Reserved: Read/Write 0s.

RootHubStatusChange: This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has

changed.

FrameNumberOverflow: Set when bit 15 of FrameNumber changes value.

UnrecoverableError (Read Only): This event is not implemented and is hard-coded to 0. Writes are ignored.

ResumeDetected: Set when HC detects resume signaling on a downstream port.

StartOfFrame: Set when the Frame Management block signals a Start of Frame event.

WritebackDoneHead: Set after the HC has written HcDoneHead to HccaDoneHead.

SchedulingOverrun: Set when the List Processor determines a Schedule Overrun has occurred.

Note: All bits are set by hardware and cleared by software.

CS5530A Datasheet(PDF) 213 Page - National Semiconductor (TI)

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