CS5530A datasheet(214/259 Pages) NSC

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214

Revision 1.1

Offset 10h-13h

HcInterruptEnable Register (R/W)

Reset Value = 00000000h

MasterInterruptEnable: This bit is a global interrupt enable. A write of 1 allows interrupts to be enabled via the specific

enable bits listed above.

OwnershipChangeEnable: 0 = Ignore; 1 = Enable interrupt generation due to Ownership Change.

29:7

Reserved: Read/Write 0s.

RootHubStatusChangeEnable: 0 = Ignore; 1 = Enable interrupt generation due to Root Hub Status Change.

FrameNumberOverflowEnable: 0 = Ignore; 1 = Enable interrupt generation due to Frame Number Overflow.

UnrecoverableErrorEnable: This event is not implemented. All writes to this bit are ignored.

ResumeDetectedEnable: 0 = Ignore; 1 = Enable interrupt generation due to Resume Detected.

StartOfFrameEnable: 0 = Ignore; 1 = Enable interrupt generation due to Start of Frame.

WritebackDoneHeadEnable: 0 = Ignore; 1 = Enable interrupt generation due to Writeback Done Head.

SchedulingOverrunEnable: 0 = Ignore; 1 = Enable interrupt generation due to Scheduling Overrun.

Note: Writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged.

Offset 14h-17h

HcInterruptDisable Register (R/W)

Reset Value = C000006Fh

MasterInterruptEnable: Global interrupt disable. A write of 1 disables all interrupts.

OwnershipChangeEnable: 0 = Ignore; 1 = Disable interrupt generation due to Ownership Change.

29:7

Reserved: Read/Write 0s.

RootHubStatusChangeEnable: 0 = Ignore; 1 = Disable interrupt generation due to Root Hub Status Change.

FrameNumberOverflowEnable: 0 = Ignore; 1 = Disable interrupt generation due to Frame Number Overflow.

UnrecoverableErrorEnable: This event is not implemented. All writes to this bit will be ignored.

ResumeDetectedEnable: 0 = Ignore; 1 = Disable interrupt generation due to Resume Detected.

StartOfFrameEnable: 0 = Ignore; 1 = Disable interrupt generation due to Start of Frame.

WritebackDoneHeadEnable: 0 = Ignore; 1 = Disable interrupt generation due to Writeback Done Head.

SchedulingOverrunEnable: 0 = Ignore; 1 = Disable interrupt generation due to Scheduling Overrun.

Note: Writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 to a bit leaves the bit unchanged.

Offset 18h-1Bh

HcHCCA Register (R/W)

Reset Value = 00000000h

31:8

HCCA: Pointer to HCCA base address.

7:0

Reserved: Read/Write 0s.

Offset 1Ch-1Ch

HcPeriodCurrentED Register (R/W)

Reset Value = 00000000h

31:4

PeriodCurrentED: Pointer to the current Periodic List ED.

3:0

Reserved: Read/Write 0s.

Offset 20h-23h

HcControlHeadED Register (R/W)

Reset Value = 00000000h

31:4

ControlHeadED: Pointer to the Control List Head ED.

3:0

Reserved: Read/Write 0s.

Offset 24h-27h

HcControlCurrentED Register (R/W)

Reset Value = 00000000h

31:4

ControlCurrentED: Pointer to the current Control List ED.

3:0

Reserved: Read/Write 0s.

Offset 28h-2Bh

HcBulkHeadED Register (R/W)

Reset Value = 00000000h

31:4

BulkHeadED: Pointer to the Bulk List Head ED.

3:0

Reserved: Read/Write 0s.

Offset 2Ch-2Fh

HcBulkCurrentED Register (R/W)

Reset Value = 00000000h

31:4

BulkCurrentED: Pointer to the current Bulk List ED.

3:0

Reserved: Read/Write 0s.

Offset 30h-33h

HcDoneHead Register (R/W)

Reset Value = 00000000h

31:4

DoneHead: Pointer to the current Done List Head ED.

3:0

Reserved: Read/Write 0s.

Table 4-26. USB BAR+Memory Offset xxh: USB Controller Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 214 Page - National Semiconductor (TI)

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