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PC87383 Datasheet(PDF) 29 Page - National Semiconductor (TI) |
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PC87383 Datasheet(HTML) 29 Page - National Semiconductor (TI) |
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29 / 77 page ![]() 3.0 Device Architecture and Configuration (Continued) Revision 1.1 29 www.national.com 3.7.3 SuperI/O Configuration 2 Register (SIOCF2) This register is reset by hardware to 63h. Location: Index 22h Type: R/W or RO Note: During initialization, bits 6 and 4 must be initialized to 0 to allow correct operation of the chip. Bit 7 6 5 4 3 2 1 0 Name PPSEL Reserved CLKRUNSEL Reserved LPCPDSEL Reserved IRRX2SEL SP1SEL Reset 0 1 1 0 0 0 1 1 Bit Description 7 PPSEL (Parallel Port Selection Control). Selects the functions connected to pins 28 and 30. 0: GPIO24, GPIO23 (default). 1: ACK, PD7. 6 Reserved. 5 CLKRUNSEL (CLKRUN Selection Control). Selects the functions connected to pin 27. This bit is reset on VDD power-up only. 0: GPO22. 1: CLKRUN (default). 4 Reserved. 3 LPCPDSEL (LPCPD Selection Control). Selects the function connected to pin 29. This bit is reset on VDD power-up only. 0: GPIO21 (default) 1: LPCPD 2 Reserved. 1 IRRX2SEL (IRRX2 Selection Control). Selects the function connected to pin 10. 0: GPIO17. 1: IRRX2_IRSL0 (default). 0 SP1SEL (Serial Port 1 Selection Control). Selects the function connected to pins 5, 3, 63, 62, 61, 60 and 59. 0: GPIO10-GPIO16. 1: RI1, DTR1_BOUT1, CTS1, SOUT1, RTS1, SIN1, DSR1, DCD1 (default). |
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