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PC87383 Datasheet(PDF) 14 Page - National Semiconductor (TI) |
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PC87383 Datasheet(HTML) 14 Page - National Semiconductor (TI) |
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14 / 77 page ![]() 1.0 Signal/Pin Connection and Description (Continued) www.national.com 14 Revision 1.1 1.4 INTERNAL PULL-UP AND PULL-DOWN RESISTORS The signals listed in Table 3 can optionally support internal pull-up (PU) and/or pull-down (PD) resistors. See Section 7.3 for the values of each resistor type. Table 3. Internal Pull-Up and Pull-Down Resistors Signal Pin(s) Type Comments General-Purpose Input/Output (GPIO) Ports GPIO00-07 15, 16, 19, 20, 21, 40, 7, 41 PU30 Programmable GPIO10-11, GPIO14-17 5, 3, 61, 60, 59, 10 PU30 Programmable GPO12-13 63, 62 PU30 Programmable GPIO21 29 PU80 Programmable GPIO20, GPIO23, GPIO24 23, 30 PU30 Programmable GPO22 27 PU80 Programmable Strap Configuration and Testability BADDR 4 PU30 Strap1 1. Active only during VDD Power-Up reset. TEST 63 PU30 Strap1 TRIS 62 PU30 Strap1 Parallel Port ACK 28 PU30 AFD_DSTRB 57 PU440 BUSY_WAIT 26 PD120 ERR 54 PU30 INIT 56 PU440 PE 25 PU220/ PD120 Programmable SLCT 24 PD30 SLIN_ASTRB 55 PU80 STB_WRITE 14 PU440 |
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