PC87383 datasheet(16/77 Pages) NSC

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2.0 Power, Reset and Clocks (Continued)

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2.2

RESET SOURCES AND TYPES

The PC87383 has the following reset sources:

• V

DD Power-Up Reset - activated when VDD is powered up.

• Hardware Reset - activated when the LRESET input is asserted (low)

2.2.1

VDD Power-Up Reset

VDD Power-Up reset is generated by an internal circuit when VDD power is turned on. VDD Power-Up reset time (tIRST) lasts

until the LRESET signal is de-asserted. The Hardware reset (LRESET) must be asserted for a minimum of 10 ms to ensure

that the PC87383 operates correctly.

External devices must wait at least tIRST before accessing the PC87383. If the host processor accesses the PC87383 during

this time, the PC87383 LPC interface ignores the transaction (that is, it does not return a SYNC handshake).

VDD Power-Up reset performs the following actions:

• Puts pins with strap options into TRI-STATE and enables their internal pull-up resistors

• Samples the logic levels of the strap pins

• Executes all the actions performed by the Hardware reset; see Section 2.2.2

2.2.2

Hardware Reset

Hardware reset is activated by assertion of LRESET input while VDD is “good”. When VDD power is off, the PC87383 ignores

the level of the LRESET input. Hardware reset performs the following actions:

• Resets all lock bits in configuration registers

• Loads default values to all the bits in the Configuration Control.

• Resets all the logical devices.

• Loads default values to all the module registers.

2.3

CLOCK DOMAINS

The PC87383 has two clock domains, as shown in Table 4.

2.3.1

LPC Domain

The LPC clock signal at the LCLK pin must become valid before the end of the Hardware reset (LRESET) (see

Section 2.2.2). This clock can be slowed down or stopped using the CLKRUN protocol.

2.3.2

48 MHz Domain

The 48 MHz clock domain is sourced either by the on-chip Clock Generator or directly by the CLKIN input pin. The Clock

Generator is fed by applying a clock source at a frequency of 14.31818 MHz. The Clock Generator generates two internal

clocks, 24 MHz and 48 MHz. After power-up or Hardware reset, the clock (Clock Generator or external clock) is disabled.

Clock Generator Functional Description

The on-chip Clock Generator starts working when it is enabled by bit 7 of the CLOCKCF register, Index 29h, i.e., when the

bit value changes from 0 to 1 (only for 14.31818 MHz clock source). Once enabled, the output clock is frozen to a steady

logic level until the clock generator provides a stable output clock that meets all requirements. Then the clock starts toggling.

On Hardware reset, the chip wakes up with the on-chip Clock Generator disabled. The input clock of the Clock Generator

may toggle regardless of the state of the LRESET pin. The Clock Generator waits for a toggling input clock.

Table 4. Clock Domains of the PC87383

Clock

Domain

Frequency

Source

Usage

LPC

Up to 33 MHz

LPC clock input (LCLK)

LPC bus interface and Conﬁguration Registers

48 MHz

On-chip Clock Generator or di-

rectly from Clock Input (CLKIN)

Legacy functions

(Serial Port, Parallel Port, Infrared)

PC87383 Datasheet(PDF) 16 Page - National Semiconductor (TI)

PC87383 Datasheet(HTML) 16 Page - National Semiconductor (TI)

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