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PC87383 Datasheet(PDF) 32 Page - National Semiconductor (TI) |
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PC87383 Datasheet(HTML) 32 Page - National Semiconductor (TI) |
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32 / 77 page ![]() 3.0 Device Architecture and Configuration (Continued) www.national.com 32 Revision 1.1 3.8 PARALLEL PORT (PP) CONFIGURATION 3.8.1 General Description The PC87383 Parallel Port supports all IEEE1284 standard communication modes: Compatibility (also known as Standard or SPP), Bi-directional (known also as PS/2), FIFO, EPP (also known as mode 4) and ECP (with an optional Extended ECP mode). The Parallel Port includes two groups of runtime registers (see Section 6.1 on page 49): • A group of 21 registers at first level offset, sharing 14 entries. Three of these registers (at offsets 403h, 404h and 405h) are used only in Extended ECP mode. • A group of four registers, used only in Extended ECP mode, is accessed by a second level offset. The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg- isters are used and which address bits are used for the base address. The Parallel Port functional block registers are shown in Section 6.1 on page 49. 3.8.2 Logical Device 1 (PP) Configuration Table 16 lists the configuration registers that affect the Parallel Port. Only the last register (F0h) is described here. See Sec- tions 3.2.3 and 3.2.4 for descriptions of the other configuration registers. Table 16. Parallel Port Configuration Registers Index Configuration Register or Action Type Reset 30h Activate (see Section 3.3.1 on page 25). R/W 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, ‘00000’. Bit 2 (for A10) must be ‘0’. R/W 02h 61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, ‘00’. For ECP mode 4 (EPP) or when using Extended registers, bit 2 (A2) must also be ‘0’. R/W 78h 70h Interrupt Number and Wake-Up on IRQ Enable register. R/W 07h 71h Interrupt Type: - Bits 7-2 are read only. - Bit 1 is a read/write bit. - Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation mode. This bit is set to 1 (level interrupt) in Extended mode and cleared (edge interrupt) in all other modes. R/W 02h 74h DMA Channel Select. R/W 04h 75h Report no second DMA assignment. RO 04h F0h Parallel Port Configuration register. R/W F2h |
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