PC87383 datasheet(39/77 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.1

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Bit

Type

Description

Reserved.

R/W or

EVDBNC (Event Debounce Enable). (Ports 0 and 1 with event detection capability). Enables

transferring the signal only after a predetermined debounce period.

0: Disabled.

1: Enabled (default).

Reserved. (Port 2 and Port 1 - bits 2 and 3).

R/W or

EVPOL (Event Polarity). (Ports 0 and 1 with event detection capability). This bit deﬁnes the polarity of

the signal that issues an interrupt from the corresponding GPIO pin (falling/low or rising/high).

0: Falling edge or low level input (default).

1: Rising edge or high level input.

Reserved. (Port 2). Always 0.

R/W or

EVTYPE (Event Type). (Ports 0 and 1 with event detection capability). This bit deﬁnes the type of the

signal that issues an interrupt from the corresponding GPIO pin (edge or level).

0: Edge input (default).

1: Level input.

Reserved. (Port 2). Always 0.

R/W1S LOCKCFP (Lock Configuration of Pin). When set to 1, this bit locks the GPIO pin conﬁguration and

data (see also Section 5.4 on page 45) by disabling writing to itself, to GPCFG register bits PUPCTL,

OUTTYPE and OUTENA, and to the corresponding bit in GPDO register. Once set, this bit can only be

cleared by Hardware reset.

0: R/W bits are enabled for write (default).

1: All bits are RO.

R/W or

PUPCTL (Pull-Up Control). This bit is used to enable/disable the internal pull-up capability of the

corresponding GPIO pin. It supports open-drain output signals with internal pull-ups and TTL input

signals.

0: Disabled.

1: Enabled (default).

R/W or

OUTTYPE (Output Type). This bit controls the output buffer type (open-drain or push-pull) of the

corresponding GPIO pin.

0: Open-drain (default).

1: Push-pull.

R/W or

OUTENA (Output Enable). This bit indicates the GPIO pin output state. It has no effect on the input

path.

0: TRI-STATE (default).

1: Output enabled.

PC87383 Datasheet(PDF) 39 Page - National Semiconductor (TI)

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