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TDA2EX Datasheet(PDF) 70 Page - Texas Instruments |
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TDA2EX Datasheet(HTML) 70 Page - Texas Instruments |
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70 / 401 page  70 TDA2E-17 SPRS969E – AUGUST 2016 – REVISED JULY 2018 www.ti.com Submit Documentation Feedback Product Folder Links: TDA2E-17 Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated (1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS. 4.3.11 QSPI NOTE For more information about UART booting, see the Initialization / Device Initialization by ROM Code / Memory Booting / SPI/QSPI Flash Devices section of the device TRM. Table 4-12. QSPI Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL qspi1_sclk QSPI1 Serial Clock IO F2 qspi1_rtclk QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer to PCB Guidelines for QSPI1 I H3 qspi1_d0 QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read and quad read modes it becomes input data pin during read phase. IO K5 qspi1_d1 QSPI1 Data[1]. Input read data in all modes. IO G2 qspi1_d2 QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during read phase IO K6 qspi1_d3 QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during read phase IO H4 qspi1_cs0 QSPI1 Chip Select[0]. This pin is Used for QSPI1 boot modes. IO G4 qspi1_cs1 QSPI1 Chip Select[1] O G3 qspi1_cs2 QSPI1 Chip Select[2] O L1 qspi1_cs3 QSPI1 Chip Select[3] O K3 4.3.12 McASP NOTE For more information, see the Serial Communication Interface / Multichannel Audio Serial Port (McASP) section of the device TRM. Table 4-13. McASP Signal Descriptions SIGNAL NAME DESCRIPTION TYPE BALL Multichannel Audio Serial Port 1 mcasp1_axr0 McASP1 Transmit/Receive Data IO D14 mcasp1_axr1 McASP1 Transmit/Receive Data IO B14 mcasp1_axr2 McASP1 Transmit/Receive Data IO C14 mcasp1_axr3 McASP1 Transmit/Receive Data IO B15 mcasp1_axr4 McASP1 Transmit/Receive Data IO A15, J25 mcasp1_axr5 McASP1 Transmit/Receive Data IO A14, J24 mcasp1_axr6 McASP1 Transmit/Receive Data IO A17, H24 mcasp1_axr7 McASP1 Transmit/Receive Data IO A16, H25 mcasp1_axr8 McASP1 Transmit/Receive Data IO A18, H21 mcasp1_axr9 McASP1 Transmit/Receive Data IO B17, K22 mcasp1_axr10 McASP1 Transmit/Receive Data IO B16, K23 mcasp1_axr11 McASP1 Transmit/Receive Data IO B18 mcasp1_axr12 McASP1 Transmit/Receive Data IO A19 mcasp1_axr13 McASP1 Transmit/Receive Data IO E17 mcasp1_axr14 McASP1 Transmit/Receive Data IO E16 |
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