TDA2EX datasheet(84/401 Pages) TI1

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TDA2E-17

SPRS969E – AUGUST 2016 – REVISED JULY 2018

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Terminal Configuration and Functions

Table 4-22. Sysboot Signal Descriptions (continued)

SIGNAL NAME

DESCRIPTION

TYPE

BALL

sysboot15

Boot Mode Configuration 15. The value latched on this pin upon porz reset release

will determine the boot mode configuration of the device.

4.3.21.2 Power, Reset, and Clock Management (PRCM)

NOTE

For more information, see PRCM section of the device TRM.

Table 4-23. PRCM Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

clkout1

Device Clock output 1. Can be used externally for devices with non-

critical timing requirements, or for debug, or as a reference clock on

GPMC as described in Table 5-47 GPMC/NOR Flash Interface

Switching Characteristics - Synchronous Mode - Default and Table 5-

49 GPMC/NOR Flash Interface Switching Characteristics -

Synchronous Mode - Alternate.

K23, L4

clkout2

Device Clock output 2. Can be used externally for devices with non-

critical timing requirements, or for debug.

H5, J25

clkout3

Device Clock output 3. Can be used xternally for devices with non-

critical timing requirements, or for debug.

H25

porz

Power on Reset (active low) input must be asserted low during a

device power up sequence or cold reset state when all supplies are

disabled. Typically, an external PMIC is the source and sets porz

high after all supplies reach valid operating levels. Asserting porz low

puts the entire device in a safe reset state.

F19

resetn

Reset (active low) input’s falling edge can trigger a device warm reset

state from an external component. This signal should be high prior to

or simultaneous with, porz rising. If the signal is not used in the

system, resetn should be pulled high with an external pull-up resistor

to vddshv3.

K24

rstoutn

Reset out (Active low) output is asserted low whenever any global

reset condition exists. After a brief delay, it will be set high upon

removal of the internal global reset condition (i.e. porz, warm reset). It

is only functional after its output buffer’s reference voltage (vddshv3)

is valid. If it is used as a reset for device peripheral components, then

it should be AND gated with porz to avoid the possibility of reset

signal glitches during a power up sequence.(2)

E20

xi_osc0

System Oscillator OSC0 Crystal input / LVCMOS clock input.

Functions as the input connection to a crystal when the internal

oscillator OSC0 is used. Functions as an LVCMOS-compatible input

clock when an external oscillator is used.

Y12

xi_osc1

Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input.

Functions as the input connection to a crystal when the internal

oscillator OSC1 is used. Functions as an LVCMOS-compatible input

clock when an external oscillator is used

AC11

xo_osc0

System Oscillator OSC0 Crystal output

AB12

xo_osc1

Auxiliary Oscillator OSC1 Crystal output

AA11

xref_clk0

External Reference Clock 0. For Audio and other Peripherals.

J25

xref_clk1

External Reference Clock 1. For Audio and other Peripherals.

J24

xref_clk2

External Reference Clock 2. For Audio and other Peripherals.

H24

xref_clk3

External Reference Clock 3. For Audio and other Peripherals.

H25

RMII_MHZ_50_CLK(1)

RMII Reference Clock (50MHz). This pin is an input when external

reference is used or output when internal reference is used.

TDA2EX Datasheet(PDF) 84 Page - Texas Instruments

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