TDA2EX datasheet(85/401 Pages) TI1

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TDA2E-17

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SPRS969E – AUGUST 2016 – REVISED JULY 2018

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Terminal Configuration and Functions

(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve

as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the

clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.

(2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it

must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.

4.3.21.3 System Direct Memory Access (SDMA)

NOTE

For more information, see the DMA Controllers / System DMA section of the device TRM.

Table 4-24. SDMA Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

dma_evt1

System DMA Event Input 1

G1, L4

dma_evt2

System DMA Event Input 2

H3, H5

dma_evt3

System DMA Event Input 3

dma_evt4

System DMA Event Input 4

4.3.21.4 Interrupt Controllers (INTC)

NOTE

For more information, see the Interrupt Controllers section of the device TRM.

Table 4-25. INTC Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

nmin_dsp

Non maskable interrupt input, active-low. This pin can be optionally routed to the

DSP NMI input or as generic input to the Arm cores. Note that by default this pin

has an internal pulldown resistor enabled. This internal pulldown should be disabled

or countered by a stronger external pullup resistor before routing to the DSP or Arm

processors.

L24

sys_nirq2

External interrupt event to any device INTC

AC10

sys_nirq1

External interrupt event to any device INTC

AB10

4.3.22 Power Supplies

NOTE

For more information, see Power, Reset, and Clock Management / PRCM Subsystem

Environment / External Voltage Inputs section of the device TRM.

Table 4-26. Power Supply Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

vdd

Core voltage domain supply

PWR

J15, J16, J18, K12,

K18, L12, L17, M11,

M13, M15, M17, N11,

N13, N15, N18, P10,

P12, P14, P16, P18,

R10, R12, R14, R16,

R17, T11, T13, T15,

T17, T9, U11, U13,

U15, U18, U9, V10,

V12, V14, V16, V18,

W10, W12, W14, W16

vpp(2)

eFuse power supply

PWR

F20

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