AD9154 datasheet(31/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 31 of 124

The PClockPeriod converts from time to PClock cycles when

needed.

PClockFactor = 4/F (Frames per PClock)

The PClockFactor converts from units of PClock cycles to frame

clock cycles, which is required to set LMFCDel in Subclass 1.

PClocksPerMF= K/PClockFactor (PClocks per LMFC Cycle)

where PClocksPerMF is the number of PClock cycles in a

multiframe cycle.

The values for PClockFactor and PClockPerMF are given per

JESD204B mode in Table 30 and Table 31.

Table 30. PClockFactor and PClockPerMF Per LMFC

JESD204B Mode ID

PClockFactor

PClockPerMF (K = 32)

PClockPerMF (K = 16)

Not applicable

Table 31. PClockFactor and PClockPerMF Per LMFC

JESD204B Mode ID

PClockFactor

PClockPerMF (K = 32)

PClockPerMF (K = 16)

N/A1

N/A means not applicable.

With Known Delays

LMFCVar and LMFCDel can be calculated directly with

information about all the system delays.

RxFixed (the fixed receiver delay in PClock cycles) and RxVar (the

variable receiver delay in PClock cycles) are found in Table 8.

TxFixed (the fixed transmitter delay in PClock cycles) and

TxVar (the variable receiver delay in PClock cycles) can be

found in the data sheet of the transmitter used. PCBFixed (the

fixed PCB trace delay in PClock cycles) is extracted from the

software. Because PCBFixed is generally much smaller than a

PClock cycle, it can be omitted. For both the PCB and transmitter

delays, convert the delays into PClock cycles.

For each lane,

MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)

FALL_COUNT_DelayLane = ceiling(RxFixed + RxVar +

TxFixed + TxVar + PCBFixed))

where, across lanes, links, and devices:

MinDelayLane is the minimum of all MinDelayLane values.

FALL_COUNT_Delay is the maximum of all

FALL_COUNT_DelayLane values.

For safety, add a guard band of 1 PClock cycle to each end of

the link delay, as shown in the following equations:

LMFCVar = (FALL_COUNT_Delay + 1) − (MinDelay − 1)

Note that if LMFCVar must be more than 10, the AD9154

cannot tolerate the variable delay in the system.

For Subclass 1,

LMFCDel = ((MinDelay − 1) × PClockFactor) % K

For Subclass 0,

LMFCDel = (MinDelay − 1) % PClockPerMF

Program the same LMFCDel and LMFCVar across all links and

devices.

See the Link Delay Setup Example, With Known Delays section

for an example calculation.

Without Known Delays

If comprehensive delay information is not available or known,

the AD9154 can read back the link latency between the LMFCRX

and the last arriving LMFC boundary in PClock cycles. Use this

information to calculate LMFCVar and LMFCDel.

For each link on each device,

1. Power up the board.

2. Follow the steps in Table 15 through Table 22 in the Device

Setup Guide section.

3. Set the subclass and perform a sync. For a one-shot sync,

perform the writes in Table 32. See the Syncing LMFC

Signals section for alternate sync modes.

4. Record DYN_LINK_LATENCY_0 (Register 0x302) as a

value of Delay for that link and power cycle.

5. Record DYN_LINK_LATENCY_1 (Register 0x303) as a

value of Delay for that link and power cycle.

Repeat Step 1 through Step 5 twenty times for each device in the

system. Keep a single list of the Delay values across all runs and

devices.

Table 32. Register Configuration and Procedure for

One-Shot Sync

Addr.

Bit.

No.

Value1

Variable

Description

0x301

Subclass

Set subclass

0x03A

0x01

Set sync mode = one-shot

sync

0x03A

0x81

Enable the sync machine

0x03A

0xC1

Arm the sync machine

SYSREF

If Subclass = 1, ensure

that at least one SYSREF±

edge is sent to the device

0x300

Enable the links

ChkSmMd

See the JESD204B Setup

section

Dual Link

See the JESD204B Setup

section

[1:0]

EnLinks

EnLinks = 3 if in DualLink

mode to enable Link 0

and Link 1; EnLinks = 1 if

not in DualLink mode to

enable Link 0

0x denotes a register value that the user must fill in. See the Variable and

Description columns for information on selecting the appropriate register

value.

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