AD9154 datasheet(81/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 81 of 124

BOARD LEVEL HARDWARE CONSIDERATIONS

POWER SUPPLY RECOMMENDATIONS

POWER

INPUT

+12V

+3.3V

AD9154

ADM7154-3.3

ADM7160-3.3

ADP1753

ADP2119

ADP1741

ADP2370

SVDD12

DVDD12

CVDD12 + PVDD12

AVDD33

IOVDD + SIOVDD33

3.8V

1.8V

STEP DOWN DC/DC

1.2MHz, 2A

BUCK

1.2Mhz/600khz

800mA

1.2V

3.3V

Figure 84. Power Supply Connections

Table 91. Power Supplies

Power Supply Domain

Voltage (V)

Circuitry

DVDD121

1.2

Digital core

PVDD122

1.2

DAC PLL

SVDD123

1.2

JESD204B receiver interface

CVDD121

1.2

DAC clocking

IOVDD

3.3

SPI interface

VTT4

1.2

VTT

SIOVDD33

3.3

Sync LVDS transmit

AVDD33

3.3

DAC

This supply requires a 1.3 V supply when operating at maximum DAC sample rates. See Table 3 for details.

This supply may be combined with CVDD12 on the same regulator with a separate supply filter network and sufficient bypass capacitors near the pins.

This supply requires a 1.3 V supply when operating at maximum interface rates. See Table 4 for details.

This supply is connected to SVDD12 and does not need separate circuitry.

The power supply domains are described in Table 91. The

power supplies can be grouped into separate PCB domains as

show in Figure 84. All the AD9154 supply domains must

remain as noise free as possible. Optimal DAC output NSD and

DAC output phase noise performance can be achieved using

linear regulators that provide excellent power supply rejection.

AVDD33, PVDD12, and CVDD12 are particularly sensitive to

supply noise.

JESD204B SERIAL INTERFACE INPUTS (SERDIN0±

TO SERDIN7±)

When considering the layout of the JESD204B serial interface

transmission lines, there are many factors to consider to

maintain optimal link performance. Among these factors are

insertion loss, return loss, signal skew, and the topology of the

differential traces.

Insertion Loss

The JESD204B specification limits the amount of insertion loss

allowed in the transmission channel (see Figure 44). The AD9154

equalization circuitry allows significantly more loss in the

channel than is required by the JESD204B specification. It is still

important that the designer of the PCB minimize the amount of

insertion loss by adhering to the following guidelines:

•

Keep the differential traces short by placing the AD9154 as

near to the transmitting logic device as possible and routing

the trace as directly as possible between the devices.

•

Route the differential pairs on a single plane using a solid

ground plane as a reference.

•

Use a PCB material with a low dielectric constant (<4) to

minimize loss, if possible.

When choosing between stripline and microstrip techniques,

consider the following: stripline has less loss (see Figure 45) and

emits less EMI, but requires the use of vias that can add complexity

to the task of controlling the impedance, whereas microstrip (see

Figure 46) is easier to implement if the component placement and

density allow routing on the top layer and eases the task of

controlling the impedance.

If using the top layer of the PCB is problematic or the advantages

of stripline are desirable, follow these recommendations:

•

Minimize the number of vias.

•

If possible, use blind vias to eliminate via stub effects and

use micro vias to minimize via inductance.

•

If using standard vias, use the maximum via length to

minimize the stub size. For example, on an 8-layer board,

use Layer 7 for the stripline pair (see Figure 85).

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