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AD9154 Datasheet(PDF) 26 Page - Analog Devices |
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AD9154 Datasheet(HTML) 26 Page - Analog Devices |
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26 / 124 page  AD9154 Data Sheet Rev. C | Page 26 of 124 If using the optional DAC PLL, also set the registers in Table 17. Table 17. Optional DAC PLL Configuration Procedure Addr. Value1 Variable Description 0x087 0x62 Optimal DAC PLL loop filter settings 0x088 0xC9 Optimal DAC PLL loop filter settings 0x089 0x0E Optimal DAC PLL loop filter settings 0x08A 0x12 Optimal DAC PLL CP settings 0x08D 0x7B Optimal DAC LDO settings for DAC PLL 0x1B0 0x00 Power DAC PLL blocks when power machine disabled 0x1B5 0xC9 Optimal DAC PLL VCO settings 0x1B9 0x24 Optimal DAC PLL calibration options settings 0x1BC 0x0D Optimal DAC PLL block control settings 0x1BE 0x02 Optimal DAC PLL VCO power control settings 0x1BF 0x8E Optimal DAC PLL VCO calibration settings 0x1C0 0x2A Optimal DAC PLL lock counter length setting 0x1C1 0x2A Optimal DAC PLL charge pump setting 0x1C4 0x7E Optimal DAC PLL varactor settings 0x1C5 0x06 Optimal DAC PLL VCO settings 0x08B 0x LODivMode See the DAC PLL Setup section 0x08C 0x RefDivMode See the DAC PLL Setup section 0x085 0x BCount See the DAC PLL Setup section Various 0x LookUpVals See the DAC PLL Setup section 0x083 0x10 Enable DAC PLL2 1 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the appropriate register value. 2 Verify that Register 0x084[1] reads back 1 after enabling the DAC PLL to indicate that the DAC PLL has locked. STEP 2: DIGITAL DATAPATH The digital datapath selects interpolation mode and the data format. Additional digital datapath capabilities are shown in Table 19. Table 18. Digital Datapath Settings Addr. Bit No. Value1 Variable Description 0x112 0x InterpMode Select the interpolation mode; see the Interpolation section. 0x110 0x 7 DataFmt DataFmt = 0 if twos complement; DataFmt = 1 if unsigned binary. 1 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the appropriate register value. There are a number of signal processing functions to be enabled if needed; these are in addition to the interpolation mode. Table 19. Digital Datapath Signal Processing Functions Feature Default Description Digital Modulation Off Modulates the data with a desired IF carrier. See the Digital Datapath section. Inverse Sinc On Improves pass-band flatness. See the Digital Datapath section. Digital Gain 0 dB Multiplies data by a factor to compensate inverse sinc usage or balance I/Q amplitude. See the Digital Datapath section. Phase Adjust Off Balances I/Q phase. See the Digital Datapath section. DC Offset Off Cancels LO leakage. See the Digital Datapath section. Group Delay 0 Controls overall latency. See the Digital Datapath section. Downstream Protection Off Protects downstream components. See the Digital Datapath section. STEP 3: TRANSPORT LAYER This section describes how to set up the JESD204B links. The desired JESD204B operating mode determines the parameters. See the JESD204B Setup section for details. Table 20. Transport Layer Settings Addr. Bit No. Value1 Variable Description 0x200 0x00 Power up the interface. 0x201 0x UnusedLanes See the JESD204B Setup section. 0x300 0x 6 CheckSumMode See the JESD204B Setup section. 3 DualLink See the JESD204B Setup section. 2 CurrentLink See the JESD204B Setup section. 0x450 0x DID Set DID to match the device ID sent by the transmitter. 0x451 0x BID Set BID to match the bank ID sent by the transmitter. 0x452 0x LID Set LID to match the lane ID sent by the transmitter. 0x453 0x 7 Scrambling See the JESD204B Setup section. [4:0] L − 12 See the JESD204B Setup section. 0x454 0x F − 12 See the JESD204B Setup section. 0x455 0x K − 12 See the JESD204B Setup section. 0x456 0x M − 12 See the JESD204B Setup section. 0x457 0x N − 12 N = 16. 0x458 0x 5 Subclass See the JESD204B Setup section. [4:0] Np − 12 Np = 16. |
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