AD9154 datasheet(37/124 Pages) AD

37 / 124 page

Data Sheet

AD9154

Rev. C | Page 37 of 124

Clock and Data Recovery

The deserializer is equipped with a CDR circuit. Instead of

recovering the clock from the JESD204B serial lanes, the CDR

recovers the clocks from the SERDES PLL. The 2.825 GHz to

6 GHz output from the SERDES PLL, shown in Figure 47, is

the input to the CDR.

Select a CDR sampling mode to generate the lane rate clock

inside the device. If the desired lane rate is greater than

5.65 GHz, half rate CDR operation must be used. If the desired

lane rate is less than 5.65 GHz, disable half rate operation. If the

lane rate is less than 2.825 GHz, disable half rate and enable 2×

oversampling to recover the appropriate lane rate clock. Table 38

breaks down the CDR sampling settings that must be set

dependent on the LaneRate.

Table 38. CDR Operating Modes

LaneRate (Gbps)

(SeeTable 4)

HALFRATE,

Bit 5

CDR_OVERSAMP,

Bit 1

CDR Oversampling

Mode

CDR Full Rate Mode

CDR Half Rate Mode

The CDR circuit synchronizes the phase that samples the data on

each serial lane independently. This independent phase adjustment

per serial interface ensures accurate data sampling and eases the

implementation of multiple serial interfaces on a PCB.

After configuring the CDR circuit, reset it and then release the

reset by writing 1 and then 0 to Register 0x206, Bit 0.

DATA LINK LAYER

The data link layer of the AD9154 JESD204B interface accepts

the deserialized data from the PHYs and deframes and descrambles

them so that data octets are presented to the transport layer to

be put into DAC samples. The architecture of the data link layer

is shown in Figure 48. It consists of a synchronization FIFO for

each lane, a crossbar switch, a deframer, and descrambler.

The AD9154 can operate as a single link or dual link, high speed

JESD204B serial data interface. When operating in dual link mode,

configure both links with the same JESD204B parameters because

they share a common device clock and system reference. All eight

lanes of the JESD204B interface handle link layer communications

such as code group synchronization, frame alignment, and frame

synchronization.

The AD9154 decodes 8-bit/10-bit control characters, allowing

marking of the start and end of the frame and alignment

between serial lanes. Each AD9154 serial interface link can issue

a synchronization request by setting its SYNCOUT0±/

SYNCOUT1± signal low. The synchronization protocol follows

Section 4.9 of the JESD204B standard. When a stream of four

consecutive /K/ symbols is received, the AD9154 deactivates the

synchronization request by setting the SYNCOUT0±/

SYNCOUT1± signal high at the next internal LMFC rising

edge. Then, it waits for the transmitter to issue a lane alignment

sequence (ILAS). During the ILAS sequence, all lanes are

aligned using the /A/ to /R/ character transition as described in

the JESD204B Serial Link Establishment section. Elastic buffers

hold early arriving lane data until the alignment character of the

latest lane arrives. At this point, the buffers for all lanes are

released and all lanes are aligned (see Figure 49).

LANE 0 DESERIALIZED

AND DESCRAMBLED DATA

LANE 7 DESERIALIZED

AND DESCRAMBLED DATA

LANE 0 DATA CLOCK

LANE 7 DATA CLOCK

SERDIN0

FIFO

SERDIN7

FIFO

CROSS

BAR

SWITCH

PCLK

DATA LINK LAYER

SPI CONTROL

SYSREF

SYNCOUTx±

SYSTEM CLOCK

PHASE DETECT

LANE0 OCTETS

LANE7 OCTETS

QUAD BYTE

DEFRAMER

(QBD)

Figure 48. Data Link Layer Block Diagram

AD9154 Datasheet(PDF) 37 Page - Analog Devices

AD9154 Datasheet(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL