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AD9154 Datasheet(PDF) 19 Page - Analog Devices |
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AD9154 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 124 page ![]() Data Sheet AD9154 Rev. C | Page 19 of 124 0 100 200 300 400 500 600 700 800 1 2 3 4 5 6 7 8 9 LANE RATE (Gbps) 1.2V, 8 LANES 1.2V, 4 LANES 1.2V, 2 LANES 1.3V, 8 LANES 1.3V, 4 LANES 1.3V, 2 LANES Figure 32. Total SERDES Supply Current (SVDD12) vs. Lane Rate: 2, 4, and 8 Lanes 180 160 140 120 100 80 60 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) 51MHz FALSE 101MHz FALSE 201MHz FALSE 401MHz FALSE 51MHz SMA100A Figure 33. Single Tone Phase Noise vs. Offset Frequency at Four Different fOUT Rates, fDAC = 2.0 GHz, PLL Off 180 160 140 120 100 80 60 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) 51MHz TRUE 101MHz TRUE 201MHz TRUE 401MHz TRUE 51MHz SMA100A Figure 34. Single Tone Phase Noise vs. Offset Frequency at Four Different fOUT Rates, fDAC = 2.0 GHz, PLL On –30 –130 –120 –110 –100 –90 –80 –70 –60 –50 –40 CENTER 180MHz #RES BW 30kHz SPAN 65.4MHz SWEEP 212.1ms #VBW 300kHz Figure 35. 1C 256 Point Quadrature Amplitude Modulation (QAM) Signal ACLR Performance, IF = 180 MHz, fDAC = 1966.08 MHz |
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