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AD9154 Datasheet(PDF) 50 Page - Analog Devices |
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AD9154 Datasheet(HTML) 50 Page - Analog Devices |
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50 / 124 page ![]() AD9154 Data Sheet Rev. C | Page 50 of 124 Table 48. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 1 Address Setting Description 0x453 0x07 or 0x87 Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled; Register 0x453, Bits[4:0] = 0x7: L = 8 lanes per link 0x454 0x01 Register 0x454, Bits[7:0] = 0x01: F = 2 octets per frame 0x455 0x0F or 0x1F Register 0x455, Bits[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe 0x456 0x03 Register 0x456, Bits[7:0] = 0x03: M = 4 converters per link 0x457 0x0F Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution 0x458 0x0F or 0x2F Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample 0x459 0x21 Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x1: S = 2 samples per converter per frame 0x45A 0x00 Register 0x45A, Bit 7 = 0: HD = 0; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0 0x46C 0xFF Register 0x46C, Bits[7:0] = 0xFF: deskew Link Lane 0 to Link Lane 7 0x476 0x02 Register 0x476, Bits[7:0] = 0x02: F = 2 octets per frame 0x47D 0xFF Register 0x47D, Bits[7:0] = 0xFF: 8 lanes enabled, set one bit per lane to enable 2 OCTETS PER LANE (F = 2) 16-BIT NIBBLE GROUP (N = 16) 2 SAMPLES PER CONVERTER PER FRAME (S = 2) DAC0 DAC1 DAC2 DAC3 SERIAL JESD204B DATA (L = 8) SAMPLES NOT SPLIT ACROSS LANES (HD = 0) NIBBLE GROUP 0 NIBBLE GROUP 1 CONV 0, SMPL 0 CONV 0, SMPL 1 D15 ... D0 (0) D15 ... D0 (1) L 0, O 0 L 0, O 1 L 1, O 0 L 1, O 1 4 CONVERTERS (M = 4) NIBBLE GROUP 2 NIBBLE GROUP 3 CONV 1, SMPL 0 CONV 1, SMPL 1 D15 ... D0 (0) D15 ... D0 (1) L 2, O 0 L 2, O 1 L 3, O 0 L 3, O 1 NIBBLE GROUP 4 NIBBLE GROUP 5 CONV 2, SMPL 0 CONV 2, SMPL 1 D15 ... D0 (0) D15 ... D0 (1) L 4, O 0 L 4, O 1 L 5, O 0 L 5, O 1 NIBBLE GROUP 6 NIBBLE GROUP 7 CONV 3, SMPL 0 CONV 3, SMPL 1 D15 ... D0 (0) D15 ... D0 (1) L 6, O 0 L 6, O 1 L 7, O 0 L 7, O 1 Figure 60. JESD204B Mode 1 Data Deframing |
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