AD9154 datasheet(82/124 Pages) AD

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AD9154

Data Sheet

Rev. C | Page 82 of 124

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For each via pair, place a pair of ground vias adjacent to them

to minimize the impedance discontinuity (see Figure 85).

LAYER 1

LAYER 2

LAYER 3

LAYER 4

LAYER 5

LAYER 6

LAYER 7

LAYER 8

MINIMIZE STUB EFFECT

GND

DIFF–

DIFF+

ADD GROUND VIAS

STANDARD VIA

Figure 85. Minimizing Stub Effect and Adding Ground Vias for Differential

Stripline Traces

Return Loss

The JESD204B specification limits the amount of return loss

allowed in a converter device and a logic device, but does not

specify return loss for the channel. However, every effort must

be made to maintain a continuous impedance on the transmission

line between the transmitting logic device and the AD9154. As

mentioned in the Insertion Loss section, minimizing the use of

vias, or eliminating them all together, reduces one of the primary

sources for impedance mismatches on a transmission line.

Maintain a solid reference beneath (for microstrip) or above

and below (for stripline) the differential traces to ensure continuity

in the impedance of the transmission line. If the stripline technique

is used, follow the guidelines listed in the Insertion Loss section

to minimize impedance mismatches and stub effects.

Another primary source for impedance mismatch is at either end

of the transmission line, where care must be taken to match the

impedance of the termination to that of the transmission line.

The AD9154 handles this internally with a calibrated termination

scheme for the receiving end of the line. See the Interface

Power-Up and Input Termination section for details on this

circuit and the calibration routine.

Signal Skew

There are many sources for signal skew, but the two sources to

consider when laying out a PCB are interconnect skew within a

single JESD204B link and skew between multiple JESD204B links.

In each case, keeping the channel lengths matched to within 15 mm

is adequate for operating the JESD204B link at speeds of up to

10.6 Gbps. Managing the interconnect skew within a single link

is fairly straightforward. Managing multiple links across multiple

devices is more complex. However, follow the 15 mm guideline

for length matching.

Topology

Structure the differential SERDINx± pairs to achieve 50 Ω to

ground for each half of the pair. Stripline vs. microstrip trade-

offs are described in the Insertion Loss section. In either case, it

is important to keep these transmission lines separated from

potential noise sources such as high speed digital signals and

noisy supplies. If using stripline differential traces, route them

using a coplanar method, with both traces on the same layer.

Although this does not offer more noise immunity than the

broadside routing method (traces routed on adjacent layers),

it is easier to route and manufacture so that the impedance

continuity is maintained. An illustration of broadside vs.

coplanar is shown in Figure 86.

Tx DIFF A

DIFF A

DIFF B

ACTIVE

Tx DIFF B

Tx ACTIVE

BROADSIDE DIFFERENTIAL Tx LINES

COPLANAR DIFFERENTIAL Tx LINES

Figure 86. Broadside vs. Coplanar Differential Stripline Routing Techniques

When considering the trace width vs. copper weight and

thickness, the speed of the interface must be considered. At

multigigabit speeds, the skin effect of the conducting material

confines the current flow to the surface. Maximize the surface

area of the conductor by making the trace width made wider to

reduce the losses. Additionally, loosely couple differential traces

to accommodate the wider trace widths. This helps reduce the

crosstalk and minimize the impedance mismatch when the traces

must separate to accommodate components, vias, connectors,

or other routing obstacles. Tightly coupled vs. loosely coupled

differential traces are shown in Figure 87.

DIFF A

DIFF B

TIGHTLY COUPLED

DIFFERENTIAL Tx LINES

LOOSELEY COUPLED

DIFFERENTIAL Tx LINES

Figure 87. Tightly Coupled vs. Loosely Coupled Differential Traces

AC Coupling Capacitors

The AD9154 requires that the JESD204B input signals be

ac-coupled to the source. These capacitors must be 100 nF and

placed as close as possible to the transmitting logic device. To

minimize the impedance mismatch at the pads, select the

package size of the capacitor so that the pad size on the PCB

matches the trace width as closely as possible.

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