AD9154 datasheet(42/124 Pages) AD

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AD9154

Data Sheet

Rev. C | Page 42 of 124

Link Delay

The link delay of a JESD204B system is the sum of fixed and

variable delays from the transmitter, channel and receiver, as

shown in Figure 53.

For proper functioning, all lanes on a link must be read during

the same LMFC period. Section 6.1 of the JESD204B

specification states that the LMFC period must be larger than

the maximum link delay.

For the AD9154, this is not necessarily the case; instead, the

AD9154 uses a local LMFC for each link (LMFCRx) that can be

delayed from the SYSREF aligned LMFC. Because the LMFC is

periodic, this can account for any amount of fixed delay. As a

result, the LMFC period must only be larger than the variation in

the link delays, and the AD9154 can achieve proper performance

with a smaller total latency. Figure 51 and Figure 52 show a case

where the link delay is larger than an LMFC period. Note that it

can be accommodated by delaying LMFCRx.

ILAS

DATA

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

EARLY ARRIVING

LMFC REFERENCE

LATE ARRIVING

LMFC REFERENCE

Figure 51. Link Delay > LMFC Period Example

ILAS

DATA

FRAME CLOCK

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

LMFCRX

LMFC_DELAY

LMFC REFERENCE FOR ALL POWER CYCLES

Figure 52. LMFC DELAY to Compensate for Link Delay > LMFC

ILAS

FIXED DELAY

VARIABLE

DELAY

POWER CYCLE

VARIANCE

DATA

LMFC

ALIGNED DATA

AT Rx OUTPUT

DATA AT

Tx INPUT

DATA

DSP

CHANNEL

LOGIC DEVICE

(JESD204B Tx)

JESD204B Rx

DAC

LINK DELAY = DELAYFIXED + DELAYVARIABLE

Figure 53. JESD204B Link Delay = Fixed Delay + Variable Delay

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