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AD9154

Data Sheet

Rev. C | Page 70 of 124

INTERRUPT REQUEST OPERATION

IRQ_EN

EVENT

DEVICE_RESET

EVENT_STATUS

INTERRUPT_SOURCE

IRQ_EN

STATUS_MODE

OTHER

INTERRUPT

SOURCES

IRQ

IRQ_RESET

Figure 74. Simplified Schematic of IRQ Circuitry

The AD9154 provides an interrupt request output signal on Pin 60

(IRQ) that can notify an external host processor of significant

device events. On assertion of the interrupt, query the device to

determine the precise event that occurred. The IRQ pin is an

open-drain, active low output. Pull the IRQ pin high external to

the device. This pin can be tied to the interrupt pins of other

devices with open-drain outputs to wire; OR these pins together.

Figure 74 shows a simplified block diagram of how the IRQ blocks

works. If IRQ_EN is low, the INTERRUPT_SOURCE signal is set

to 0. If IRQ_EN is high, any rising edge of EVENT causes the

INTERRUPT_SOURCE signal to be set high. If any INTERRUPT_

SOURCE signal is high, the IRQ pin is pulled low. INTERRUPT_

SOURCE can be reset to 0 by either an IRQ_RESET signal or a

DEVICE_RESET.

Depending on STATUS_MODE, the EVENT_STATUS bit reads

back event or INTERRUPT_SOURCE. The AD9154 has several

IRQ register blocks, which can monitor up to 75 events (depending

on device configuration). Certain details vary by IRQ register

block as described in Table 75. Table 76 shows which registers the

IRQ_EN, IRQ_RESET, and STATUS_MODE signals in Figure 74

are coming from, as well as the address where EVENT_STATUS

is read back.

Table 75. IRQ Register Block Details

EVENT

Reported

EVENT_STATUS

0x01F to 0x026

Per chip

INTERRUPT_SOURCE if

IRQ is enabled, if not, it

is EVENT

0x46D to 0x46F; 0x470

to 0x473; 0x47A

Per link and

lane

INTERRUPT_SOURCE if

IRQ is enabled, if not, 0

0x47B[4]

Per link

INTERRUPT_SOURCE if

IRQ is enabled, if not, 0

INTERRUPT SERVICE ROUTINE

Interrupt request management starts by selecting the set of event

flags that require host intervention or monitoring. Enable the

events that require host action so that the host is notified when

they occur. For events requiring host intervention upon IRQ

activation, run the following routine to clear an interrupt request:

1. Read the status of the event flag bits that are being monitored.

2. Disable the interrupt by writing 0 to IRQ_EN.

3. Read the event source. For Register 0x01F to

other events, see their registers.

4. Perform any actions that may be required to clear the cause of

the event. In many cases, no specific actions may be required.

5. Verify that the event source is functioning as expected.

6. Clear the interrupt by writing 1 to IRQ_RESET.

7. Enable the interrupt by writing 1 to IRQ_EN.

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