AD9154 datasheet(79/124 Pages) AD

79 / 124 page

Data Sheet

AD9154

Rev. C | Page 79 of 124

STEP 3: TRANSPORT LAYER

Table 85. Link 0 Transport Layer

Command

Address

Value

Description

0x200

0x00

Power up the interface

0x201

0x00

Enable all lanes

0x300

0x08

Bit 3 = 1 for dual link, Bit 2 = 0 to

access Link 0 registers

0x450

0x00

Set the device ID to match Tx

(0x00 in this example)

0x451

0x00

Set the bank ID to match Tx (0x00

in this example)

0x452

0x00

Set the lane ID to match Tx (0x00

in this example)

0x453

0x83

Set descrambling and L = 4

(in n − 1 notation)

0x454

0x00

Set F = 1 (in n − 1 notation)

0x455

0x1F

Set K = 32 (in n − 1 notation)

0x456

0x01

Set M = 2 (in n − 1 notation)

0x457

0x0F

Set N = 16 (in n − 1 notation)

0x458

0x2F

Set Subclass 1 and NP = 16 (in

n − 1 notation)

0x459

0x20

Set JESD 204B Version and S = 1

(in n − 1 notation)

0x45A

0x80

Set HD = 1

0x45D

0x45

Set checksum for Lane 0

0x46C

0x0F

Deskew Lane 0 to Lane3

0x476

0x01

Set F (not in n − 1 notation)

0x47D

0x0F

Enable Lane 0 to Lane 3

Table 86. Link 1 Transport Layer

Command

Address

Value

Description

0x300

0x0C

Bit 3 = 1 for dual link, Bit 2 = 1 to

access registers for Link 1

0x450

0x00

Set the device ID to match Tx

(0x00 in this example)

0x451

0x00

Set the bank ID to match Tx (0x00

in this example)

0x452

0x04

Set the lane ID to match Tx (0x04

in this example)

0x453

0x83

Set descrambling and L = 4 (in

n − 1 notation)

0x454

0x00

Set F = 1 (in n − 1 notation)

0x455

0x1F

Set K = 32 (in n − 1 notation)

0x456

0x01

Set M = 2 (in n − 1 notation)

0x457

0x0F

Set N = 16 (in n − 1 notation)

0x458

0x2F

Set Subclass 1 and NP = 16 (in

n − 1 notation)

0x459

0x20

Set JESD 204B and S = 1 (in n − 1

notation)

0x45A

0x80

Set HD

0x45D

0x45

Set checksum for Lane 0

0x46C

0x0F

Deskew Lane 4 to Lane 7

0x476

0x01

Set F (not in n − 1 notation)

0x47D

0x0F

Enable Lane 4 to Lane 7

STEP 4: PHYSICAL LAYER

Table 87. Physical Layer

Command

Address

Value

Description

0x2A7

0x01

Autotune PHY setting

0x2AE

0x01

Autotune PHY setting

0x314

0x01

SERDES SPI configuration

0x230

0x28

Configure CDRs in half rate mode

0x206

0x00

Resets CDR logic

0x206

0x01

Release CDR logic reset

0x289

0x04

Configure PLL divider to 1 along

with PLL required configuration

0x284

0x62

Optimal SERDES PLL loop filter

0x285

0xC9

Optimal SERDES PLL loop filter

0x286

0x0E

Optimal SERDES PLL loop filter

0x287

0x12

Optimal SERDES PLL charge pump

0x28A

0x7B

Optimal SERDES PLL VCO LDO

0x28B

0x00

Optimal SERDES PLL PD

0x290

0x89

Optimal SERDES PLL VCO

0x291

0x4C

Optimal SERDES PLL VCO

0x294

0x24

Optimal SERDES PLL charge pump

0x296

0x1B

Optimal SERDES PLL VCO

0x297

0x0D

Optimal SERDES PLL VCO

0x299

0x02

Optimal SERDES PLL PD

0x29A

0x8E

Optimal SERDES PLL VCO

0X29C

0x2A

Optimal SERDES PLL charge pump

0x29F

0x7E

Optimal SERDES PLL VCO

0x2A0

0x06

Configure SERDES PLL VCO

0x280

0x01

Enable SERDES PLL

0x281

0x01

Verify that Bit 0 reads back high

for SERDES PLL lock

0x268

0x62

Set equalizer mode to low power

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