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AD9154

Data Sheet

Rev. C | Page 12 of 124

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PVDD12

CLK+

CLK–

PVDD12

SYSREF+

SYSREF–

PVDD12

NOTES

1. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE.

2. DNC = DO NOT CONNECT.

PVDD12

TXEN0

TXEN1

DVDD12

SERDIN0+

SERDIN0–

SVDD12

SERDIN1+

SERDIN1–

SVDD12

PDP OUT1

59 PDP OUT0

60 IRQ

61 RESET

62 SDO

63 SDIO

64 SCLK

65 CS

66 IOVDD

PVDD12

DNC

DVDD12

SERDIN7+

SERDIN7–

SVDD12

SERDIN6+

SERDIN6–

SVDD12

VTT

SVDD12

VTT

SVDD12

AD9154

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 12. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 4, 7, 8, 9, 10,

56, 57

PVDD12

1.2 V Clock Supplies.

CLK+

PLL Reference/Clock Input, Positive. When the PLL is used, this pin is the positive reference clock input.

When the PLL is not used, this pin is the positive device clock input. This pin is self biased and must be

ac-coupled.

CLK−

PLL Reference/Clock Input, Negative. When the PLL is used, this pin is the negative reference clock input.

When the PLL is not used, this pin is the negative device clock input. This pin is self biased and must be

ac-coupled.

SYSREF+

Timing Reference Input, Positive. This pin is used in JESD204B Subclass 1 systems and is self biased,

ac-coupled, or dc-coupled.

SYSREF−

Timing Reference Input, Negative. This pin is used in JESD204B Subclass 1 systems and is self biased,

ac-coupled, or dc-coupled.

TXEN0

Transmit enable for DAC0 and DAC1. CMOS levels are determined with respect to IOVDD.

TXEN1

Transmit Enable for DAC2 and DAC3. CMOS levels are determined with respect to IOVDD.

13, 14, 53

DVDD12

1.2 V Digital Supplies.

SERDIN0+

Serial Channel Input 0, Positive. CML compliant. SERDIN0+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN0−

Serial Channel Input 0, Negative. CML compliant. SERDIN0− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

17, 20, 22, 28,

31, 32, 33, 36,

39, 45, 47, 50

SVDD12

1.2 V JESD204B Receiver Supplies.

SERDIN1+

Serial Channel Input 1, Positive. CML compliant. SERDIN1+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN1−

Serial Channel Input 1, Negative. CML compliant. SERDIN1− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

21, 25, 42, 46

VTT

1.2 V Termination Voltage Pins.

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