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AD9154

Data Sheet

Rev. C | Page 36 of 124

Clock Multiplication Relationships

The following clocks rates are used throughout the rest of the

JESD204B section. The relationship between any of the clocks

can be derived from the following equations:

DataRate = (DACRate)/(InterpolationFactor)

LaneRate = (20 × DataRate × M)/L

ByteRate = LaneRate/10

where:

M is the JESD204B parameter for converters per link.

L is the JESD204B parameter for lanes per link.

F is the JESD204B parameter for octets per frame per lane.

This comes from 8-bit/10-bit encoding, where each byte is

represented by 10 bits.

PClockRate = ByteRate/4

The processing clock is used for a quad-byte decoder.

FrameRate = ByteRate/F

where F is defined as (bytes per frame) per lane.

PClockFactor = FrameRate/PClockRate = 4/F

SERDES PLL

Functional Overview of the SERDES PLL

The independent SERDES PLL uses integer-N techniques to

achieve clock synthesis. The entire SERDES PLL is integrated

on chip, including the VCO and the loop filter. The SERDES

PLL VCO operates over the range of 5.65 GHz to 12 GHz.

In the SERDES PLL, a VCO divider block divides the VCO

clock by 2 to generate a 2.825 GHz to 6 GHz quadrature clock

for the deserializer cores. This clock is the input to the CDR

block described in the Clock and Data Recovery section.

The reference clock to the SERDES PLL is always running at a

frequency of fREF = 1/40 of the lane rate = PClockRate. This clock is

divided by a DivFactor to deliver a clock to the PFD block that

is between 35 MHz and 80 MHz. Table 37 includes the respective

SERDES_PLL_DIV_MODE register settings for each of the

desired DivFactor options available.

Table 37. SERDES PLL Divider Settings

LaneRate (Gbps)

(see Table 4)

Divide by

(DivFactor)

SPI_CDR_OVERSAMP

CDR

Oversampling

Mode

CDR Full Rate

Mode

CDR Half Rate

Mode

To enable the SERDES PLL, first set the PLL divider register

according to Table 37, then enable the SERDES PLL by writing

Confirm that the SERDES PLL is working by reading

locked. If Register 0x281, Bit 3 = 1, the SERDES PLL is successfully

calibrated. If Register 0x281, Bit 4 or Register 0x281, Bit 5 are high,

the PLL hits the upper or lower end of its calibration band and

must be recalibrated by writing 0 and then 1 to Register 0x280,

Bit 2.

SERDES PLL Fixed Register Writes

To optimize the SERDES PLL across all operating conditions,

the following register writes to the following locations are

recommended: 0x284, 0x285, 0x286, 0x287, 0x28A, 0x28B,

0x290, 0x291, 0x294, 0x296, 0x297, 0x299, 0x29A, 0x29C,

0x29F, and 0x2A0 as shown in Table 21.

SERDES PLL IRQ

SERDES PLL lock and lost signals are available as IRQ events.

Use Register 0x01F, Bit 3 and Bit2 to enable these signals, and then

use Register 0x023, Bit 3 and Bit 2 to read back their statuses and

reset the IRQ signals. See the Interrupt Request Operation

section for more information.

LC VCO

5.65GHz TO 12GHz

CHARGE

PUMP

PFD

80MHz

MAX

DOWN

fREF

BIT RATE ÷ 40

3.2mA

CALIBRATION

CONTROL

BITS

VCO

LDO

÷2

÷80

2.825GHz TO 6GHz

OUTPUT

I Q

DivFactor

(1, 2, 4)

Figure 47. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block

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