AD9154 datasheet(99/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 99 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

ENABLE_SYNTH

Synthesizer Enable. The bit initiates the start-up

sequence of the DAC PLL. The start-up sequence is as

follows:

0x0

R/W

1. Enable the bias currents.

2. Enable DAC LDO.

3. Wait for LDO to settle.

4. Calibrate DAC PLL charge pump (The DAC charge

pump will only calibrate upon the first setting of

ENABLE_SYNTH).

5. Calibrate the band of the PLL.

6. Settle and lock.

0 Disable synthesizer including all currents and

calibration codes.

1 Power up synthesizer and initiate calibration sequence.

[3:0]

RESERVED

Reserved.

0x0

0x084

DACPLL-

STATUS

CP_

OVERRANGE_H

Charge Pump High Overrange. This bit indicates that

the charge pump voltage is too high and a

recalibration must be applied.

0x0

0 Control voltage not too high.

1 Control voltage too high.

CP_

OVERRANGE_L

Charge Pump Low Overrange. This bit indicates that

the charge pump voltage is too low and a

recalibration must be applied.

0x0

0 Control voltage not too low.

1 Control VOLTAGE too low.

CP_CAL_VALID

Charge Pump Calibration Valid. This bit indicates that

the charge pump has been successfully calibrated.

The selection as to whether the charge pump needs

to be calibrated upon startup can be found in

0x0

0 If CP_CAL_EN low, this stays low.

1 If CP_CAL_EN high (def), this happens when charge

pump is calibrated.

VCO_CAL_

PROGRESS

VCO Calibration in Progress. This bit is high if the VCO

calibration is currently occurring. If this bit is high for

more than 1 sec there is something wrong with the

VCO calibration.

0x0

0 VCO not calibrating.

1 VCO calibrating.

[3:2]

RESERVED

Reserved.

0x0

RFPLL_LOCK

PLL Lock bit. This bit is set high by the PLL once the

PLL has achieved lock for the count set by

LOCK_MODE bits in Register 0x1C0.

0x0

1 PLL locked.

0 PLL unlocked.

RESERVED

Reserved.

0x0

0x085

DACINTEGER

WORD0

[7:0]

BCOUNT

Bits[7:0] of the Integer Tuning Word. This bit controls

the integer feedback divider for the DAC PLL. The

frequency of the DAC clock can be determined by

the following equations:

0x6

R/W

fDAC = fREF/(REFDIVMODE ) × 2 × BCount

fVCO = fREF /(REFDIVMODE ) × 2 × BCount ×

LODivMode

The minimum value is 6.

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