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AD9154 Datasheet(PDF) 102 Page - Analog Devices |
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AD9154 Datasheet(HTML) 102 Page - Analog Devices |
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102 / 124 page  AD9154 Data Sheet Rev. C | Page 102 of 124 Addr. Name Bits Bit Name Settings Description Reset Access 0x117 FTW3 [7:0] FTW3 NCO Frequency Tuning Word, FTW[31:24]. 0x0 R/W 0x118 FTW4 [7:0] FTW4 NCO Frequency Tuning Word, FTW[39:32]. 0x0 R/W 0x119 FTW5 [7:0] FTW5 NCO Frequency Tuning Word, FTW[47:40]. 0x10 R/W 0x11A NCO_PHASE_ OFFSET0 [7:0] NCO_PHASE_ OFFSET0 NCO Phase Offset, NCO_PHASE_OFFSET[7:0]. 0x0 R/W 0x11B NCO_PHASE_ OFFSET1 [7:0] NCO_PHASE_ OFFSET1 NCO Phase Offset, NCO_PHASE_OFFSET[15:8]. 0x0 R/W 0x11C NCO_ PHASEADJ[7:0] [7:0] PHASEADJ[7:0] Phase Compensation Word, PHASE_ADJ[7:0]. 0x0 R/W 0x11D NCO_ PHASEADJ [12:8] [7:0] PHASEADJ[12:8] Phase Compensation Word, PHASE_ADJ[12:8]. 0x0 R/W 0x11F TXEN_SM_0 [7:6] PA_FALL PA Fall Control. 0x2 R/W [5:4] PA_RISE PA Rises Control. 0x0 R/W 3 RESERVED Reserved. 0x0 R 2 GP_PA_ON_ INVERT External Modulator Polarity Invert. 0x0 R/W 1 GP_PA_CTRL External PA Control. Enabled by default to allow external mod control instead of sync signal through this pin. 0x1 R/W 0 TXEN_SM_EN Enable TXEN State Machine. 0x1 R/W 0x121 TXEN_SM_2 [7:0] RISE_COUNT_0 0xF R/W 0x122 TXEN_SM_3 [7:0] RISE_COUNT_1 0x0 R/W 0x123 TXEN_SM_4 [7:0] FALL_COUNT_0 0xFF R/W 0x124 TXEN_SM_5 [7:0] FALL_COUNT_1 0xFF R/W 0x12D DEVICE_ CONFIG_REG0 [7:0] DEVICE_ CONFIG_0 Must Be Set to 0x8B for Proper Digital Datapath Configuration. 0x46 R/W 0x12F DIE_TEMP_ CTRL0 [7:1] RESERVED Reserved. 0x10 R/W 0 AUXADC_ ENABLE 1 = Enable AUXADC Block. 0x0 R/W 0x132 DIE_TEMP0 [7:0] DIE_TEMP_LSB AUXADC Readback Value Bits[7:0], LSB. 0x0 R 0x133 DIE_TEMP1 [7:0] DIE_TEMP_MSB AUXADC Readback Value Bits[15:8], MSB. 0x0 R 0x134 DIE_TEMP_ UPDATE [7:1] RESERVED Reserved. 0x0 R 0 DIE_TEMP_ UPDATE Die Temperature Update. When updated, new temperature code is received. 0x0 R/W 0x135 DC_OFFSET_ CTRL [7:1] RESERVED Reserved. 0x0 R 0 DC_OFFSET_ON 1 = Enable DC Offset Module. 0x0 R/W 0x136 IPATH_DC_OFF- SET_1PART0 [7:0] IPATH_DC_ OFFSET_1PART0 LSB of First Part of DC Offset Value for I Path. 0x0 R/W 0x137 IPATH_DC_OFF- SET_1PART1 [7:0] IPATH_DC_ OFFSET_1PART1 MSB of First Part of DC Offset Value for I Path. 0x0 R/W 0x138 QPATH_DC_ OFFSET_ 1PART0 [7:0] QPATH_DC_ OFFSET_1PART0 LSB of First Part of DC Offset Value for Q Path. 0x0 R/W 0x139 QPATH_DC_ OFFSET_ 1PART1 [7:0] QPATH_DC_ OFFSET_1PART1 MSB of First Part of DC Offset Value for Q Path. 0x0 R/W 0x13A IPATH_DC_ OFFSET_2PART [7:5] RESERVED Reserved. 0x0 R [4:0] IPATH_DC_ OFFSET_2PART Second Part Of DC Offset Value For I Path. 0x0 R/W |
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