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AD9154 Datasheet(PDF) 106 Page - Analog Devices

Part # AD9154
Description  Digital-to-Analog Converter
PDF  124 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9154 Datasheet(HTML) 106 Page - Analog Devices

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AD9154
Data Sheet
Rev. C | Page 106 of 124
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x1BE
DACPLLTE
[7:4]
RESERVED
Reserved.
0x0
R
3
VCO_PDO_VR
Varactor Reference Power-down Override.
0x0
R/W
2
VCO_PDO_VRTCF
Varactor Temperature Coefficient Power-Down
0x0
R/W
1
VCO_PDO_
CALTCF
Calibration Temperature Coefficient Power-Down.
0x0
R/W
0
VCO_PDO_
VCOBUF
VCO Buffer PD Override.
0x0
R/W
0x1BF
DACPLLTF
7
I_CAL_EN
VCO Band Calibration Enable.
0x1
R/W
[6:4]
I_ALC_WAIT_D
VCO calibration wait for ALC cal from band change.
0x0
R/W
[3:2]
I_CAL_COUNT
Calibration Count Length.
0x3
R/W
[1:0]
FDBCK_DELAY
Feedback Clock Advance.
0x1
R/W
0x1C0
DACPLLT10
[7:6]
RESERVED
Reserved.
0x0
R
5
USE_NEW_CAL
Use new calibrator.
0x1
R/W
0 use old calibrator.
1 use new calibrator.
4
DOUBLE_F0_CAL_
CNT
Increase calibrator count by 2×—Old calibrator
machine.
0x0
R/W
[3:2]
LOCKDETECT_CO
UNT
Counter length for Lock detector.
0x3
R/W
[1:0]
LOCK_MODE
Lock Detector Mode.
0x2
R/W
0x1C1
DACPLLT11
7
RESERVED
Reserved.
0x0
R
6
CP_LVL_DET_PD
Level detector power-down.
0x0
R/W
[5:3]
CP_VL_LOW
Low Level detect voltage.
0x2
R/W
[2:0]
CP_VL_HIGH
High Level detection point.
0x5
R/W
0x1C2
DACPLLT15
7
SDM_BP
Bypass Sigma Delta.
0x1
R/W
6
SDM_PD
Power-Down SDM.
0x0
R/W
[5:4]
RESERVED
Reserved.
0x0
R
[3:0]
SDM_PROG
Program SDM.
0x0
R/W
0x1C3
DACPLLT16
7
RESERVED
Reserved.
0x0
R
6
SDM_PROG3
SIF Clock.
0x0
R/W
5
SDM_PROG2
SIF Preset Bar.
0x0
R/W
[4:0]
SDM_PROG1
SIF Address.
0x0
R/W
0x1C4
DACPLLT17
7
RESERVED
Reserved.
0x0
R
[6:4]
VCO_VAR_REF_
TCF
Varactor Reference Temperature Coefficient.
0x3
R/W
[3:0]
VCO_VAR_OFF
Varactor Offset.
0x3
R/W
0x1C5
DACPLLT18
[7:4]
RESERVED
Reserved.
0x0
R
[3:0]
VCO_VAR_REF
VCO Varactor Reference.
0x8
R/W
0x200
MASTER_PD
[7:1]
RESERVED
Reserved.
0x0
R
0
SPI_PD_MASTER
Power down the entire JESD204B Rx analog (all eight
channels + bias).
0x1
R/W
0x201
PHY_PD
[7:0]
UNUSEDLANES
SPI override to power down the individual PHYs.
0x0
R/W
Set Bit x to power down the corresponding SERDINx±
PHY.
0x203
GENERIC_PD
[7:2]
RESERVED
Reserved.
0x0
R
1
SPI_SYNC1_PD
Power down LVDS buffer for SYNCOUT0±.
0x0
R/W
0
SPI_SYNC2_PD
Power down LVDS buffer for SYNCOUT1±.
0x0
R/W
0x206
CDR_RESET
[7:1]
RESERVED
Reserved.
0x0
R
0
SPI_CDR_RESETN
Resets the digital control logic for all PHYs.
0x1
R/W
0 CDR logic is reset.
1 CDR logic is operational.



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