AD9154 datasheet(107/124 Pages) AD

107 / 124 page

Data Sheet

AD9154

Rev. C | Page 107 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x230

CDR_

OPERATING_

MODE_REG_0

[7:6]

RESERVED

Reserved.

0x0

R/W

HALFRATE

Enables half rate CDR operation.

0x1

R/W

0 Disables CDR half rate operation, data rate ≤6 Gbps.

1 Enables CDR half rate operation, data rate > 6 Gbps.

[4:2]

RESERVED

Reserved.

0x0

R/W

CDR_OVERSAMP

Enables Oversampling of the Input Data. Set to 1

when 1.44 Gbps ≤ lane rate ≤ 2.88 Gbps.

0x0

R/W

RESERVED

Reserved.

0x0

R/W

0x268

EQ_BIAS_REG

[7:6]

EQ_POWER_

MODE

Controls the equalizer power/insertion loss

capability.

0x1

R/W

0 Normal Mode.

1 Low Power.

[5:0]

RESERVED

Reserved.

0x32

R/W

0x280

SYNTH_

ENABLE_

CNTRL

[7:3]

RESERVED

Reserved.

0x0

SPI_RECAL_

SYNTH

Set this bit high to re-run all of the SERDES PLL

calibration routines.

0x0

R/W

Set this bit low again to allow for additional re-

calibrations. Rising edge causes the calibration.

RESERVED

Reserved.

0x0

R/W

SPI_ENABLE_

SYNTH

Enable the SERDES PLL.

0x0

R/W

Setting this bit turns on all currents and proceeds to

calibrate the PLL.

Make sure reference clock and division ratios are

correct before enabling this bit.

0x281

PLL_STATUS

[7:6]

RESERVED

Reserved.

0x0

SPI_CP_OVER_

RANGE_HIGH_RB

Applies if SPI_VCO_OUTPUT_LEVEL = 0. If set, the CP

output is above CP Level Threshold High.

0x0

0 Charge pump output is below

CP_LEVEL_THRESHOLD_HIGH.

1 Charge pump output is above

CP_LEVEL_THRESHOLD_HIGH.

SPI_CP_OVER_

RANGE_LOW_RB

Applies if SPI_VCO_OUTPUT_LEVEL = 0. If set, the CP

output is below CP Level Threshold Low.

0x0

0 Charge pump output is above

CP_LEVEL_THRESHOLD_LOW.

1 Charge pump output is below

CP_LEVEL_THRESHOLD_LOW.

SPI_CP_CAL_

VALID_RB

This bit tells the user if the charge pump cal has

completed.

0x0

0 Charge pump calibration is not valid.

1 Charge pump calibration is valid.

SPI_VCO_CAL_IN

_PROGRESS_RB

This bit set indicates that a VCO calibration is

running.

0x0

0 VCO calibration is not running.

1 VCO calibration is running.

SPI_CURRENTS_

READY_RB

0x0

0 PLL bias currents are not ready.

1 PLL bias currents are ready.

SPI_PLL_LOCK_

If set, the synth locked in the number of clock cycles

set by Lock Detect Count.

0x0

0 PLL is not locked.

1 PLL is locked.

AD9154 Datasheet(PDF) 107 Page - Analog Devices

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