AD9154 datasheet(111/124 Pages) AD

111 / 124 page

Data Sheet

AD9154

Rev. C | Page 111 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x302

DYN_LINK_

LATENCY_0

[7:5]

RESERVED

Reserved.

0x0

[4:0]

DYN_LINK_

LATENCY_0

Link 0 Dynamic Link Latency.

0x0

Latency between current deframer LMFC and the

global LMFC.

0x303

DYN_LINK_

LATENCY_1

[7:5]

RESERVED

Reserved.

0x0

[4:0]

DYN_LINK_

LATENCY_1

Link 1 Dynamic Link Latency.

0x0

Latency between current deframer LMFC and the

global LMFC.

0x304

LMFC_

DELAY_0

[7:5]

RESERVED

Reserved.

0x0

[4:0]

LMFCDEL0

Delay in Frame clock cycles for global LMFC for Link 0.

0x0

R/W

0x305

LMFC_

DELAY_1

[7:5]

RESERVED

Reserved.

0x0

[4:0]

LMFCDEL1

Delay in Frame clock cycles for global LMFC for Link 1.

0x0

R/W

0x306

LMFCVAR0

[7:5]

RESERVED

Reserved.

0x0

[4:0]

LMFCVAR0

Location in Rx LMFC where JESD204B words are read

out from buffer.

0x6

R/W

This setting should not be more than 10.

0x307

LMFCVAR1

[7:5]

RESERVED

Reserved.

0x0

[4:0]

LMFCVAR1

Location in Rx LMFC where JESD204B words are read

out from buffer.

0x6

R/W

This setting should not be more than 10.

0x308

XBAR_LN_0_1

[7:6]

RESERVED

Reserved.

0x0

[5:3]

XBARVAL1

Logic Lane 1 Source. Selects a physical lane to be

mapped onto Logical Lane 1.

0x1

R/W

Data is from SERDINx±.

[2:0]

XBARVAL0

Logic Lane 0 Source. Selects a physical lane to be

mapped onto Logical Lane 0.

0x0

R/W

Data is from SERDINx±.

0x309

XBAR_LN_2_3

[7:6]

RESERVED

Reserved.

0x0

[5:3]

XBARVAL3

Logic Lane 3 Source. Selects a physical lane to be

mapped onto Logical Lane 3.

0x3

R/W

Data is from SERDINx±.

[2:0]

XBARVAL2

Logic Lane 2 Source. Selects a physical lane to be

mapped onto Logical Lane 2.

0x2

R/W

Data is from SERDINx±.

0x30A

XBAR_LN_4_5

[7:6]

RESERVED

Reserved.

0x0

[5:3]

XBARVAL5

Logic Lane 5 Source. Selects a physical lane to be

mapped onto Logical Lane 5.

0x5

R/W

Data is from SERDINx±.

[2:0]

XBARVAL4

Logic Lane 4 Source. Selects a physical lane to be

mapped onto Logical Lane 4.

0x4

R/W

Data is from SERDINx±.

0x30B

XBAR_LN_6_7

[7:6]

RESERVED

Reserved.

0x0

[5:3]

XBARVAL7

Logic Lane 7 Source. Selects a physical lane to be

mapped onto Logical Lane 7.

0x7

R/W

Data is from SERDINx±.

[2:0]

XBARVAL6

Logic Lane 6 Source. Selects a physical lane to be

mapped onto Logical Lane 6.

0x6

R/W

Data is from SERDINx±.

0x30C

FIFO_

STATUS_

REG_0

[7:0]

LANE_FIFO_FULL

FIFO Full Flags for Each Logical Lane. A full FIFO

indicates an error in the JESD204B configuration or

with a system clock. If the FIFO for Lane x is full, Bit x

in this register will be high.

0x0

AD9154 Datasheet(PDF) 111 Page - Analog Devices

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