AD9154 datasheet(112/124 Pages) AD

112 / 124 page

AD9154

Data Sheet

Rev. C | Page 112 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x30D

FIFO_STATUS_

REG_1

[7:0]

LANE_FIFO_

EMPTY

FIFO Empty Flags for Each Logical Lane. An empty

FIFO indicates an error in the JESD204B configuration

or with a system clock. If the FIFO for Lane x is empty,

Bit x in this register will be high.

0x0

0x312

SYNCB_

GEN_1

[7:6]

RESERVED

Reserved.

0x0

R/W

[5:4]

SYNCB_ERR_DUR

Duration of SYNCOUTx± Low for Error. The duration

applies to both SYNCOUT0 and SYNCOUT1. A sync

error is asserted at the end of a multiframe

whenever one or more disparity, not in table or

unexpected control character errors are

encountered.

0x0

R/W

½ PCLK cycle.

1 PCLK cycle.

2 PCLK cycles.

[3:0]

RESERVED

Reserved.

0x0

R/W

0x314

SPI_SYNC_

CTRL

[7:1]

RESERVED

Reserved.

0x0

SPI_SYNC_CLK_

SEL

SERDES SPI Configuration.

0x0

R/W

1 Setting in PHY Layer setup.

0x315

PHY_PRBS_

TEST_EN

[7:0]

PHY_TEST_EN

Set Bit x to enable the PHY test for Lane x.

0x0

R/W

0x316

PHY_PRBS_

TEST_CTRL

RESERVED

Reserved.

0x0

[6:4]

PHY_SRC_ERR_

CNT

Report Lane Error Count.

0x0

R/W

[3:2]

PHY_PRBS_

PAT_SEL

To select PRBS pattern for PHY BER test.

0x0

R/W

0 PRBS7.

1 PRBS15.

2 PRBS31.

3 Not used.

PHY_TEST_START

To start and stop the PHY PRBS test.

0x0

R/W

0 test not started.

1 test started.

PHY_TEST_RESET

Reset PHY PRBS test state machine, and error

counters.

0x0

R/W

0 not reset.

1 reset.

0x317

PHY_PRBS_

TEST_THRES-

HOLD_LOBITS

[7:0]

PHY_PRBS_

THRESHOLD_

LOBITS

Bits[7:0] of the 24-bit threshold value to set the error

flag for PHY PRBS test.

0x0

R/W

0x318

PHY_PRBS_

TEST_THRESH

OLD_MIDBITS

[7:0]

PHY_PRBS_

THRESHOLD_

MIDBITS

Bits[15:8] of the 24-bit threshold value to set the

error flag for PHY PRBS test.

0x0

R/W

0x319

PHY_PRBS_

TEST_THRES-

HOLD_HIBITS

[7:0]

PHY_PRBS_

THRESHOLD_

HIBITS

Bits[23:16] of the 24-bit threshold value to set the

error flag for PHY PRBS test.

0x0

R/W

0x31A

PHY_PRBS_

TEST_ERRCNT_

LOBITS

[7:0]

PHY_PRBS_ERR_

CNT_LOBITS

Bits[7:0] of the 24-bit reported PHY BERT error count

from selected lane.

0x0

0x31B

PHY_PRBS_

TEST_ERRCNT_

MIDBITS

[7:0]

PHY_PRBS_ERR_

CNT_MIDBITS

Bits[15:8] of the 24-bit reported PHY BERT error count

from selected lane.

0x0

AD9154 Datasheet(PDF) 112 Page - Analog Devices

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