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AD9154 Datasheet(PDF) 115 Page - Analog Devices

Part # AD9154
Description  Digital-to-Analog Converter
PDF  124 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9154 Datasheet(HTML) 115 Page - Analog Devices

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Data Sheet
AD9154
Rev. C | Page 115 of 124
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
[4:0]
NP_RD
Np is the Total Number of Bits/Sample.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
= 16 bits per sample.
0x409
S_REG
[7:5]
JESDV_RD
JESDV is the JESD204 Version.
0x0
R
Link information received on lane 0 as specified in
section 8.3 of JESD204B.
0 JESD204A.
1 JESD204B.
[4:0]
S_RD
S is the Number of Samples/Converter per Frame
Cycle.
0x0
R
Link information received on lane 0 as specified in
section 8.3 of JESD204B.
0 One sample per converter per frame.
1 Two samples per converter per frame.
0x40A
HD_CF_REG
7
HD_RD
HD is the High Density Format.
0x0
R
Refer to Section 5.1.3 of JESD204B standard.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
0 Low density mode.
1 High density mode.
[6:5]
RESERVED
Reserved.
0x0
R
[4:0]
CF_RD
CF is the Number of Control Words per Frame Clock
Period per Link.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Must be 0 to be compatible to the AD9154.
0x40B
RES1_REG
[7:0]
RES1_RD
Reserved Field 1.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
0x40C
RES2_REG
[7:0]
RES2_RD
Reserved Field 2.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
0x40D
CHECKSUM_
REG
[7:0]
LANE0CHECKSU
M_RD
Checksum for Lane 0.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
0x40E
COMPSUM0_
REG
[7:0]
FCMP0_RD
Computed Checksum for Lane 0.
0x0
R
The JESD204B Rx computes the checksum of the link
information received on Lane 0 as specified in
Section 8.3 of JESD204B. The computation method is
set by the CHECKSUMMODE bit (Register 0x300[6])
and should match the likewise calculated checksum
in Register 0x40D.
0x412
LID1_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID1_RD
Lane Identification for Lane 1.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
0x415
CHECKSUM1_
REG
[7:0]
FCHK1_RD
Checksum for Lane 1.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
0x416
COMPSUM1_
REG
[7:0]
FCMP1_RD
Computed Checksum for Lane 1. See description for
Register 0x40E.
0x0
R
0x41A
LID2_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID2_RD
Lane Identification for Lane 2.
0x0
R



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