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AD9154 Datasheet(PDF) 113 Page - Analog Devices |
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AD9154 Datasheet(HTML) 113 Page - Analog Devices |
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113 / 124 page  Data Sheet AD9154 Rev. C | Page 113 of 124 Addr. Name Bits Bit Name Settings Description Reset Access 0x31C PHY_PRBS_ TEST_ERRCNT_ HIBITS [7:0] PHY_PRBS_ERR_ CNT_HIBITS Bits[23:16] of the 24-bit reported PHY BERT error count from selected lane. 0x0 R 0x31D PHY_PRBS_ TEST_STATUS [7:0] PHY_PRBS_PASS Each bit is for the corresponding lane. 0xFF R Report PHY BERT pass/fail for each lane. 0x32C SHORT_TPL_ TEST_0 [7:6] RESERVED Reserved. 0x0 R [5:4] SHORT_TPL_SP_ SEL Short Transport Layer Sample Select. Select which sample to check from a specific DAC. 0x0 R/W 0 Sample 0. 1 Sample 1. 2 Sample 2. 3 Sample 3. [3:2] SHORT_TPL_M_ SEL Short Transport Layer Test DAC Select. Select which DAC to check. 0x0 R/W 0 DAC 0. 1 DAC 1. 2 DAC 2. 3 DAC 3. 1 SHORT_TPL_TEST _RESET Short Transport Layer Test Reset. Resets the result of short transport layer test at SHORT_TPL_DIFF. 0x0 R/W 0 Not reset. 1 Reset. 0 SHORT_TPL_ TEST_EN Short Transport Layer Test Enable. Enable short transport layer test. 0x0 R/W 0 Disable. 1 Enable. 0x32D SHORT_TPL_ TEST_1 [7:0] SHORT_TPL_REF_ SP_LSB Short Transport Layer Reference Sample LSB. This is the lower 8 bits of expected DAC sample. It compares with the received DAC sample at the output of JESD204B Rx. 0x0 R/W 0x32E SHORT_TPL_ TEST_2 [7:0] SHORT_TPL_REF_ SP_MSB Short Transport Layer Test Reference Sample MSB. This is the upper 8 bits of expected DAC sample. It compares with the received sample at JESD Rx output. 0x0 R/W 0x32F SHORT_TPL_ TEST_3 [7:1] RESERVED Reserved. 0x0 R 0 SHORT_TPL_FAIL Short Transport Layer Test Fail. This bit shows if the selected DAC sample matches the reference sample. If they match test pass; otherwise test fail. 0x0 R 0 Test pass. 1 Test fail. 0x333 DEVICE_CON- FIG_REG2 [7:0] RESERVED Must be set to 0x1 for correct JESD204B receiver operation. 0x0 R/W 0x334 JESD_BIT_ INVERSE_CTRL [7:0] INVLANES Logic Lane Invert. Set Bit x high to invert the JESD204B deserialized data on Logical Lane x. 0x0 R/W 0x400 DID_REG [7:0] DID_RD DID is the Device ID No. 0x0 R Link information received on Lane 0 as specified in Section 8.3 of JESD204B. 0x401 BID_REG [7:4] ADJCNT_RD ADJCNT is the Adjustment Resolution to DAC LMFC. 0x0 R Link information received on Lane 0 as specified in Section 8.3 of JESD204B. [3:0] BID_RD BID is the Bank ID—Extension to DID. 0x0 R Link information received on Lane 0 as specified in Section 8.3 of JESD204B. |
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