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AD9154 Datasheet(PDF) 116 Page - Analog Devices

Part # AD9154
Description  Digital-to-Analog Converter
PDF  124 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9154 Datasheet(HTML) 116 Page - Analog Devices

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AD9154
Data Sheet
Rev. C | Page 116 of 124
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x41D
CHECKSUM2_
REG
[7:0]
FCHK2_RD
Checksum for Lane 2.
0x0
R
0x41E
COMPSUM2_
REG
[7:0]
FCMP2_RD
Computed Checksum for Lane 2. See description for
Register 0x40E.
0x0
R
0x422
LID3_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID3_RD
Lane Identification for Lane 3.
0x0
R
0x425
CHECKSUM3_
REG
[7:0]
FCHK3_RD
Checksum for Lane 3.
0x0
R
0x426
COMPSUM3_
REG
[7:0]
FCMP3_RD
Computed Checksum for LANE 3 (see description for
Register 0x40E).
0x0
R
0x42A
LID4_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID4_RD
Lane Identification for Lane 4.
0x0
R
0x42D
CHECKSUM4_
REG
[7:0]
FCHK4_RD
Checksum for Lane 4
0x0
R
0x42E
COMPSUM4_
REG
[7:0]
FCMP4_RD
Computed Checksum for Lane 4 (see description for
Register 0x40E).
0x0
R
0x432
LID5_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID5_RD
Lane Identification for Lane 5.
0x0
R
0x435
CHECKSUM5_
REG
[7:0]
FCHK5_RD
Checksum for Lane 5.
0x0
R
0x436
COMPSUM5_
REG
[7:0]
FCMP5_RD
Computed Checksum for Lane 5 (see description for
Register 0x40E).
0x0
R
0x43A
LID6_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID6_RD
Lane Identification for Lane 6.
0x0
R
0x43D
CHECKSUM6_
REG
[7:0]
FCHK6_RD
Checksum for Lane 6.
0x0
R
0x43E
COMPSUM6_
REG
[7:0]
FCMP6_RD
Computed Checksum for Lane 6 (see description for
Register 0x40E).
0x0
R
0x442
LID7_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LID7_RD
Lane Identification for Lane 7.
0x0
R
0x445
CHECKSUM7_
REG
[7:0]
FCHK7_RD
Checksum for Lane 7.
0x0
R
0x446
COMPSUM7_
REG
[7:0]
FCMP7_RD
Computed Checksum for Lane 7 (see description for
Register 0x40E).
0x0
R
0x450
ILS_DID
[7:0]
DID
DID is the Device ID Number.
0x0
R/W
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Must be set to value read in Register 0x400.
0x451
ILS_BID
[7:4]
ADJCNT
ADJCNT is the Adjustment Resolution to DAC LMFC.
0x0
R/W
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
[3:0]
BID
BID is the Bank ID—Extension to DID.
0x0
R/W
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Must be set to value read in Register 0x401[3:0].
0x452
ILS_LID0
7
RESERVED
Reserved.
0x0
R
6
ADJDIR
ADJDIR is the Direction to Adjust DAC LMFC.
0x0
R/W
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
5
PHADJ
PHADJ is the Phase Adjustment Request To DAC.
0x0
R/W
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
[4:0]
LID0
LID0 is the Lane identification for Lane 0.
0x0
R/W
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.



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