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AD9154 Datasheet(PDF) 118 Page - Analog Devices

Part # AD9154
Description  Digital-to-Analog Converter
PDF  124 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9154 Datasheet(HTML) 118 Page - Analog Devices

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AD9154
Data Sheet
Rev. C | Page 118 of 124
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x45D
ILS_CHECKSUM [7:0]
LANE0-
CHECKSUM
Checksum for Lane 0.
0x45
R/W
The checksum for the values programmed into
Register 0x450 to Register 0x45C must be calculated
according to section 8.3 of the JESD204B spec and
written here [SUM(Register 0x450 – Register 0x45C)
% 256 ].
0x46B
ERRCNTRMON
7
RESERVED
Reserved.
0x0
R
[6:4]
LANESEL
Lane Select for JESD204B Error Counter.
0x0
W
Writing these bits selects the JESD lane to monitor
the error type designated by the register write to
CNTRSEL (Bits 1:0]) BADDISCNTR, NITCNTR and
UEKCCNTR error counters in each lane are accessed
via indirect addressing. To read a counter value, the
LANESEL and CNTRSEL are first written, then the read
back accesses the desired counter.
0 Selects Lane 0.
1 Selects Lane 1.
3 Selects Lane 2.
3 Selects Lane 3.
4 Selects Lane 4.
5 Selects Lane 5.
6 Selects Lane 6.
7 Selects Lane 7.
[3:2]
RESERVED
Reserved.
0x0
R
[7:0]
READERRORCNTR
Read JESD204B Error Counter.
0x0
R
After selecting the lane and error counter by writing
to LANESEL (Bits[6:4]) and CNTRSEL (1:0), the selected
error counter is read back here.
[1:0]
CNTRSEL
JESD204B Error Counter Select.
0x0
W
Writing these bits allows the readback of the following
JESD204B errors for the lane designated by the register
write to LANESEL (Bits[6:4]). To read a counter value, the
LANESEL and CNTRSEL are first written, then the read
back access the desired counter.
0
BADDISCNTR: bad running disparity counter.
1
NITCNTR: not in table error counter.
2
UCCCNTR: Unexpected control character counter.
0x46C
LANEDESKEW
[7:0]
LANEDESKEW
Lane Deskew.
0xF
R/W
Enabled on a per lane basis by writing 1 to the
appropriate bit position: Bits[7:0] map to Lane 7 to
Lane 0. Note that in dual link mode, only Bits[3:0] are
used for each link.
1: Deskew enabled for Lane 0.
1: Deskew enabled for Lane 1.
1: Deskew enabled for Lane 2.
1: Deskew enabled for Lane 3.
1: Deskew enabled for Lane 4.
1: Deskew enabled for Lane 5.
1: Deskew enabled for Lane 6.
1: Deskew enabled for Lane 7.



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