AD9154 datasheet(121/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 121 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

BADCHECKSUM_

MASK

Bad Checksum Mask.

0x0

1 If there is a bad checksum (Register 0x472) on any

lane, IRQ is pulled low.

BADCHECKSUM_

FLAG

Bad Checksum Flag.

0x0

1 Bad checksum on at least one lane. Read Register 0x472

to determine which lanes are in error.

RESERVED

Reserved.

0x0

CODEGRPSYNC_

FLAG

1 Code Group Sync Flag. Code group sync failed on at

least one lane. Read Register 0x470 to determine

which lanes are in error.

0x0

Code group sync failed on at least one lane. Read

CODEGRPSYNC_

MASK

1 Code Group Sync Machine Mask. If code group sync

(Register 0x470) fails on any lane, IRQ is pulled low.

0x0

0x47B

SYNCASSERT-

IONMASK

BADDIS_S

Bad Disparity Error on Sync.

0x0

R/W

1 Asserts a sync request on SYNCOUTx± when the bad

disparity character count reaches the threshold in

NIT_S

Not in table Error on Sync.

0x0

R/W

1 Asserts a sync request on SYNCOUTx± when the not

in table character count reaches the threshold in

UCC_S

Unexpected Control Character Error on Sync.

0x0

R/W

1 Asserts a sync request on SYNCOUTx± when the

unexpected control character count reaches the

threshold in Register 0x47C.

CMM

Configuration Mismatch IRQ. If CMM_ENABLE is high,

this bit latches on a rising edge and pull IRQ low.

When latched, write a 1 to clear this bit. If

CMM_ENABLE is low, this bit is non-functional.

0x0

R/W

1 Link Lane 0 configuration registers (Register 0x450 to

settings (Register 0x400 to Register 0x40D).

Configuration Mismatch IRQ. If CMM_ENABLE is high,

this bit latches on a rising edge and pull IRQ low.

When latched, write a 1 to clear this bit. If

CMM_ENABLE is low, this bit is non-functional.

CMM_ENABLE

Configuration Mismatch IRQ Enable.

0x1

R/W

1 Enables IRQ generation if a configuration mismatch

is detected.

0 Configuration mismatch IRQ disabled.

Mismatch IRQ disabled.

[2:0]

RESERVED

Reserved.

0x0

0x47C

ERRORTHRES

[7:0]

ETH

Error Threshold. Bad disparity, not in table, and

unexpected control character errors are counted and

compared to the error threshold value. When the

count reaches the threshold, either an IRQ is

generated or the SYNCOUTx± signal is asserted per

the mask register settings, or both. Function is

performed in all lanes.

0xFF

R/W

0x47D

LANEENABLE

[7:0]

LANE_ENA

Lane Enable. Setting Bit x enables Link Lane x.

0xF

R/W

This register must be programmed before receiving

the code group pattern for proper operation.

0x47E

RAMP_ENA

[7:1]

RESERVED

Reserved.

0x0

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