AD9154 datasheet(119/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 119 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x46D

BADDISPARITY

RSTIRQ_DIS

Reset BADDIS IRQ counter for lane selected via

Bits[2:0] by writing 1 to this bit.

0x0

DISABLE_ERRCNT

_DIS

Disable the BADDIS error counter for lane selected

via Bits[2:0] by writing 1 to this bit.

0x0

RSTERRCNTR_DIS

Reset BADDIS error counter for lane selected via

Bits[2:0] by writing 1 to this bit.

0x0

[4:3]

RESERVED

Reserved.

0x0

[7:0]

BADDIS

Bad Disparity Character Error (BADDIS).

0x0

Each bit corresponds to each lane. The error count

can be accessed via Register 0x46B. Note that in dual

link mode, only Bits[3:0] are used for each link.

1 BadDisparitycharacter error count has reached the

threshold count of Register 0x7C for any lane with its

corresponding bit set when reading this register.

0 Bad Disparity character error count has Not reached

the threshold count.

[2:0]

LANEADDR_DIS

Lane Address for functions described in Bits[7:5]

0x0

0x46E

NITDISPARITY

RSTIRQ_NIT

Reset IRQ for lane selected via Bits[2:0] by writing 1

to this bit.

0x0

DISABLE_

ERRCNT_NIT

Disable the error counter for lane selected via

Bits[2:0] by writing 1 to this bit.

0x0

RSTERRCNTR_NIT

Reset error counter for lane selected via Bits[2:0] by

writing 1 to this bit.

0x0

[4:3]

RESERVED

Reserved.

0x0

[7:0]

NITD

Not In Table Disparity Character Error (NITD).

0x0

Each bit corresponds to each lane. The error count

can be accessed via Register 0x46B. Note that in dual

link mode, only Bits[3:0] are used for each link.

[2:0]

LANEADDR_NIT

Lane Address for functions described in Bits[7:5].

0x0

0x46F

UNEXPECTEDK

CHAR

RSTIRQ_K

Reset IRQ for lane selected via Bits[2:0] by writing 1

to this bit.

0x0

DISABLE_ERRCNT

Disable the error counter for lane selected via

Bits[2:0] by writing 1 to this bit.

0x0

RSTERRCNTR_K

Reset error counter for lane selected via Bits[2:0] by

writing 1 to this bit.

0x0

[4:3]

RESERVED

Reserved.

0x0

[2:0]

LANEADDR_K

Lane Address for functions described in Bits[7:5].

0x0

0x470

CODEGRP-

SYNCFLG

[7:0]

CODEGRPSYNC

Code Group Sync Flag (from each instantiated lane)

0x0

R/W

Writing 1 to Bit 7 resets the IRQ. The associated IRQ

flag is located in Register 0x470[0].

A loss of CODEGRPSYNC triggers Sync Request

assertion. Refer to the SYSREF, SYNCOUT, and the

Deterministic Latency section.

1 on Bit x of this register = synchronization was

achieved on lane L.

0 on Bit x of this register = synchronization was lost

on Lane x.

0x471

FRAMESYNC-

FLG

[7:0]

FRAMESYNC

Frame Sync Flag (from each instantiated lane).

0x0

R/W

This register indicates the live status for each lane.

Writing 1 to Bit 7 resets the IRQ.

A loss of Frame Sync automatically initiates a

synchronization sequence.

0x472

GOODCHK-

SUMFLG

[7:0]

GOOD-

CHECKSUM

Good Check Sum flag (from each instantiated lane.)

0x0

R/W

Writing 1 to Bit 7 resets the IRQ. The associated IRQ

flag is located in Register 0x470[2].

AD9154 Datasheet(PDF) 119 Page - Analog Devices

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