AD9154 datasheet(34/124 Pages) AD

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AD9154

Data Sheet

Rev. C | Page 34 of 124

Table 35. Dual Link JESD204B Operating Modes for Link 0 and Link 1

Mode

Parameter

M (Converter Counts)

L (Lane Counts)

S (Samples per Converter per Frame)

F (Octets/Frame per Lane)

Example Clock for 10 Gbps Lane Rate

PClock (MHz)

250

Frame Clock (MHz)

1000

500

250

1000

500

Sample Clock (MHz)

1000

500

250

1000

500

EQUALIZER

CDR

1:40

DESERIALIZER

FROM SERDES PLL

SPI CONTROL

TERMINATION

SERDINx±

Figure 42. Deserializer Block Diagram

PHYSICAL LAYER

The physical layer of the JESD204B interface, hereafter referred

to as the deserializer, has eight identical channels. Each channel

consists of the terminators, an equalizer, a CDR circuit, and the

1:40 demux function (see Figure 42).

JESD204B data is input to the AD9154 via the SERDINx± 1.2 V

differential input pins as per the JESD204B specification.

Power-Down Unused PHYs

Note that any unused and enabled lanes unnecessarily consume

extra power. Each lane that is not in use (SERDINx±) must be

powered off by writing a 1 to the corresponding bit of PHY_PD

(Register 0x201).

Interface Power-Up and Input Termination

Before using the JESD204B interface, it must be powered up by

setting Register 0x200[0] = 0. In addition, each physical lane that is

not being used (SERDINx±) must be powered down. To do so,

set the corresponding Bit x for Physical Lane x in Register 0x201 to

0 if the physical lane is being used, and to 1 if it is not being used.

The AD9154 autocalibrates the input termination to 50 Ω.

PHY 6, and PHY 7. Register 0x2AE controls autocalibration for

PHY 2, PHY 3, PHY 4, and PHY 5. The PHY termination

autocalibration routine is shown in Table 36.

Table 36. PHY Termination Autocalibration Routine

Address

Value

Description

0x2A7

0x01

Autotune PHY terminations

0x2AE

0x01

Autotune PHY terminations

The input termination voltage of the DAC is sourced externally

via the VTT pins (Pin 21, Pin 25, Pin 42, and Pin 46). Set VTT by

connecting it to SVDD12. It is recommended that the JESD204B

inputs be ac-coupled to the JESD204B transmit device using

100 nF capacitors.

Receiver Eye Mask

The AD9154 complies with the JESD204B specification regarding

the receiver eye mask and can capture data that complies with

this mask without equalization. With equalization enabled, the

AD9154 can reliably capture from signals with much smaller

eye openings. Figure 43 shows the receiver eye mask normalized to

the data rate interval with a 600 mV VTT swing. See the JESD204B

specification for more information regarding the eye mask and

permitted receiver eye opening.

525

–55

–525

0.5

1.00

0.35

0.65

TIME (UI)

LV-OIF-11G-SR TX EYE MASK

(3.125Mbps ≥ UI ≤ 12.5Gbps)

Figure 43. Receiver Eye Mask

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