AD9154 datasheet(47/124 Pages) AD

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Data Sheet

AD9154

Rev. C | Page 47 of 124

Configuration Parameters

The AD9154 modes refer to the link configuration parameters

for L, K, M, N, NP, S, and F. Table 46 provides the description

and addresses for these settings.

Table 46. Configuration Parameters

JESD204B

Setting

Description

Address

[Bits]

L − 1

Number of lanes − 1.

0x453[4:0]

F1 − 1

Number of ((octets per frame) per

lane) − 1.

0x454[7:0]

K − 1

Number of frames per multiframe − 1.

0x455[4:0]

M − 1

Number of converters − 1.

0x456[7:0]

N − 1

Converter bit resolution − 1.

0x457[4:0]

NP − 1

Bit packing per sample − 1.

0x458[4:0]

S − 1

Number of ((samples per converter)

per frame) − 1.

0x459[4:0]

High density format. Set to 1 if F = 1.

Leave at 0 if F ≠ 1.

0x45A[7]

F parameter, in ((octets per frame) per

lane).

0x476[7:0]

DID

Device ID. Match the device ID sent

by the transmitter.

0x450[7:0]

BID

Bank ID. Match the bank ID sent by

the transmitter.

0x451[3:0]

LID0

Lane ID for Lane 0. Match the lane ID

sent by the transmitter on Logical

Lane 0.

0x452[4:0]

JESDVER

JESD Version. Match the version sent

by the transmitter (0x0 = JESD204A,

0x1 = JESD204B).

0x459[7:5]

F must be programmed in two places: Register 0x454, Bits[7:0] and

Data Flow Through the JESD204B Receiver

The link configuration parameters determine how the serial bits

on the JESD204B receiver interface are deframed and passed on

to the DACs as data samples. Figure 58 shows a detailed flow of

the data through the various hardware blocks for Mode 4 (L = 4,

M = 2, S = 1, F = 1). Simplified flow diagrams for all other modes

are provided in Figure 59 through Figure 67.

Single and Dual Link Configuration

The AD9154 uses the settings contained in Table 44 and Table 45.

Mode 0 to Mode 10 can be used for single link operation.

Mode 4 to Mode 10 can also be used for dual link operation.

To use dual link mode, set DUALLINK (Register 0x300, Bit 3) to 1.

In dual link mode, Link 1 must be programmed with identical

parameters to Link 0. To write to Link 1, set SEL_REG_MAP_1

(Register 0x300, Bit 2) to 1.

If single link mode is being used, a small amount of power can

be saved by powering down the output buffer for SYNCOUT1±,

which can be done by setting Register 0x203, Bit 0 = 1.

Checking Proper Configuration

As a convenience, the AD9154 provides some quick configuration

checks. Register 0x030, Bit 5 is high if an illegal LMFCDELx is

used. Register 0x030, Bit 3 is high if an unsupported combination

of L, M, F, or S is used. Register 0x030, Bit 2 is high if an illegal

K is used. Register 0x030, Bit 1 is high if an illegal SUBCLASSV

is used.

Deskewing and Enabling Logical Lanes

After proper configuration, the logical lanes must be deskewed and

enabled to capture data.

Set Bit x in Register 0x46C to 1 to deskew Logical Lane x and to 0 if

that logical lane is not being used. Then, set Bit x in Register 0x47D

to 1 to enable Logical Lane x and to 0 if that logical lane is not

being used.

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