AD9154 datasheet(120/124 Pages) AD

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AD9154

Data Sheet

Rev. C | Page 120 of 124

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x473

INITLANE-

SYNCFLG

[7:0]

INITIALLANESYNC

Initial Lane Sync Flag (from each instantiated lane).

0x0

R/W

Writing 1 to Bit 7 resets the IRQ. The associated IRQ

flag is located in Register 0x470[2].

Loss of synchronization is also reported on SYNCOUT.

Refer to the SYSREF, SYNCOUT, and the Deterministic

Latency section.

0x476

CTRLREG1

[7:0]

F_AGAIN

F is the number of octets per frame.

0x1

R/W

Settings of 1, 2, and 4 are valid. Refer to Table 15 and

Table 16.

0x477

CTRLREG2

ILAS_MODE

ILAS Test Mode.

0x0

R/W

Defined in Section 5.3.3.8 of JESD204B specification.

1 JESD204B receiver is constantly receiving ILAS frames.

0 Normal link operation.

[6:4]

RESERVED

Reserved.

0x0

THRESHOLD_

MASK_EN

Threshold Mask Enable. Set this bit if using

SYNC_ASSERTION_MASK (Register 0x47B[7:5]).

0x0

R/W

[2:0]

RESERVED

Reserved.

0x0

0x478

KVAL

[7:0]

KSYNC

Number of 4 × K multiframes during ILAS.

0x1

R/W

Sets the number of multiframes to send lane alignment

sequence during the initial lane alignment.

1 = 4 × K multiframes.

0x47A

IRQVECTOR

BADDIS_FLAG

Bad Disparity Error Count.

0x0

1 Bad disparity character count reached ERRORTHRESH

(Register 0x47C) on at least one lane. Read Register

0x46D to determine which lanes are in error.

BADDIS_MASK

Bad Disparity Mask.

0x0

1 If the bad disparity count reaches ERRORTHRESH on

any lane, IRQ is pulled low.

NITD_MASK

Not in Table Mask.

0x0

1 If the not in table character count reaches

ERRORTHRESH on any lane, IRQ is pulled low.

NITD_FLAG

Not in Table Error Count.

0x0

1 Not in table character count reached ERRORTHRESH

(Register 0x47C) on at least one lane. Read Register

0x46E to determine which lanes are in error.

UEKC_FLAG

Unexpected Control Character Error Count.

0x0

1 Unexpected control character count reached

ERRORTHRESH (0x47C) on at least one lane. Read

UEKC_MASK

Unexpected Control Character Mask.

0x0

1 If the unexpected control character count reaches

ERRORTHRESH on any lane, IRQ is pulled low.

RESERVED

Reserved.

0x0

INITIALLANESYNC

_FLAG

Unexpected Control Character Error Count.

0x0

1 Unexpected control character count reached

ERRORTHRESH (Register 0x47C) on at least one lane.

Read Register 0x46F to determine which lanes are in

error.

INITIALLANESYNC

_MASK

Initial Lane Sync Mask.

0x0

If initial lane sync (Register 0x473) fails on any

lane, IRQ is pulled low.

AD9154 Datasheet(PDF) 120 Page - Analog Devices

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