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AD9154 Datasheet(PDF) 114 Page - Analog Devices

Part # AD9154
Description  Digital-to-Analog Converter
PDF  124 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9154 Datasheet(HTML) 114 Page - Analog Devices

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AD9154
Data Sheet
Rev. C | Page 114 of 124
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x402
LID0_REG
7
RESERVED
Reserved.
0x0
R
6
ADJDIR_RD
ADJDIR is the Direction to Adjust DAC LMFC.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
5
PHADJ_RD
PHADJ is the Phase Adjustment Request to DAC.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
[4:0]
LID0_RD
LID0 is the Lane Identification for Lane 0.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
0x403
SCR_L_REG
7
SCR_RD
SCR is the Tx Scrambling Status.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
0 Scrambling is disabled.
1 Scrambling is enabled.
[6:5]
RESERVED
Reserved.
0x0
R
[4:0]
L_RD
L is the Number of Lanes per Converter Device.
0x0
R
Link information received on lane 0 as specified in
section 8.3 of JESD204B.
0 1 lane per converter device.
1 2 lanes per converter device.
3 4 lanes per converter device.
0x404
F_REG
[7:0]
F_RD
F is the Number of Octets Per Frame.
0x0
R
Settings of 1, 2, and 4 are valid.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
0 1 octet per frame.
1 2 octets per frame.
3 4 octets per frame.
0x405
K_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
K_RD
K is the Number of Frames per Multiframe.
0x0
R
Settings of 16 or 32 are valid.
Link information received on lane 0 as specified in
section 8.3 of JESD204B.
01111 = 16.
11111 = 32.
0x406
M_REG
[7:0]
M_RD
M is the Number of Converters/Device.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Must be 1,2, or 4 to be compatible with AD9154
0 1 converter per device.
1 2 converters per device.
3 4 converters per device.
0x407
CS_N_REG
[7:6]
CS_RD
CS is the Number of Control Bits/Sample.
0x0
R
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Must be 0 to be compatible with AD9154.
5
RESERVED
Reserved.
0x0
R
[4:0]
N_RD
N = converter resolution.
0x0
R
0x408
NP_REG
[7:5]
SUBCLASSV_RD
SUBCLASSV is the Device SubClass Version.
0x0
R
Link information received on lane 0 as specified in
section 8.3 of JESD204B.



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