GC4016 datasheet(49/83 Pages) TI

49 / 83 page

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August 27, 2001

GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

This document contains information which may be changed at any time without notice

ADDRESS 19:

Final Shift Register, Suggested default = 0x34

ADDRESS 20:

Channel Map Register, Suggested default = 0xE4

This register maps down converter channels to output (resampler) channels. For most applications this will be a simple map

of channel A to output channel 0, channel B to output channel 1, etc. However, for multichannel modes (see Section 3.4) such

as SPLITIQ two or even four channels may be directed to the same output channel.

ADDRESS 21:

Add-To Register, Suggested default = 0x70

When processing complex input signals partial results are computed in adjacent channels that must be summed together to

produce a meaningful result. This control bit informs the resampler to save the data presented to it’s input and add it to the next

sample presented (if the chip is properly set up this will be from the next channel). In this manner the real and imaginary portions

of the input are rejoined prior to resampling.

ADDRESS 22:

Resampler Clock Divide Register, Suggested default = 0x00

In many applications only a small portion of the resampler computational throughput is required. Power can be reduced by

dividing the clock driving the resampler. The resampler clock rate is 2*FCK/(1+RES_CLK_DIV). Caution must be used to avoid

BIT

TYPE

NAME

DESCRIPTION

0-3 LSB

R/W

FINAL_SHIFT

The final shift up applied to all output channels before rounding and outputting.

Legal values are 0-15.

4-5

R/W

ROUND

Round the output to 12 (ROUND=0), 16 (ROUND=1), 20 bits (ROUND=2) or 24

bits (ROUND=3). Note, the data is output from the resampler in all cases as 24

bit words. Rounding is into the MSBs, unused LSBs of the 24 bit output words

are not cleared. The chip’s output word size is set by BITS_PER_WORD in the

output page, not by ROUND.

R/W

TAG_22

Two bit tag mode. Replaces the 2 LSBs of the 24 bit resampler output word with

the 2 LSBs of the tag words. Changes the 24 bit round mode (ROUND=3), if it is

used, to be a 22 bit round mode.

7 (MSB

R/W

Unused

BIT

TYPE

NAME

DESCRIPTION

0-1 LSB

R/W

CHAN_MAP_A

The channel map for channel A. This tells the hardware which output channel

the results of down converter channel A should be directed to.

2-3

R/W

CHAN_MAP_B

The channel map for down converter channel B.

4-5

R/W

CHAN_MAP_C

The channel map for down converter channel C.

6-7 MSB

R/W

CHAN_MAP_D

The channel map for down converter channel D.

BIT

TYPE

NAME

DESCRIPTION

0 LSB

R/W

ADD_A_TO_B

Add down converter channel A to down converter channel B.

R/W

ADD_B_TO_C

Add down converter channel B to down converter channel C.

R/W

ADD_C_TO_D

Add down converter channel C to down converter channel D.

R/W

ADD_D_TO_NEXT_A

Not useful. Must be set to zero.

4-6

R/W

RATIO_SYNC

Changes to the ratio map (address 23) are synchronized to this sync source.

7 MSB

R/W

Unused

BIT

TYPE

NAME

DESCRIPTION

0-7

R/W

RES_CLK_DIV

Resampler clock division.

GC4016 Datasheet(PDF) 49 Page - Texas Instruments

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