GC4016 datasheet(20/83 Pages) TI

20 / 83 page

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August 27, 2001

GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

This document contains information which may be changed at any time without notice

gain is:

where RES_SUM is the sum of the QTAP coefficients.

3.5.6 By-Passing the Resampler

The resampler is bypassed by using a configuration

which has h0 set to 1024, all other taps set to zero, NMULT

set to 7, NO_SYM_RES set to 1, FINAL_SHIFT set to 5, and

RATIO set to 226 (0x04000000). Note that the NDELAY term

in the RES_GAIN equation shown above does not apply in

this case and should be set to unity in the gain equation.

3.5.7 Adaptive Ratio Change

The ratio maps (address 23) can be used to dynamically

adjust each channel’s resampling ratio. Four different ratios

can be loaded into the chip. The ratio map indicates which

ratio is to be used by which channel. This feature can be

used to lock the resampling to a desired output timing by

adaptively selecting ratios which are slightly larger or smaller

or equal to the desired ratio. If the timing needs to be

accelerated, then the larger ratio is selected, if the timing is

correct, then the exact ratio is used and if the timing needs to

be retarded, then a smaller ratio is used. The ratio change

can be synchronized using the RATIO_SYNC control in

address 21.

3.6

OVERALL GAIN

The overall gain of the chip is a function of the amount

of blanking (NZEROS), the decimation programmed into the

chip (N), the scale circuit setting in the CIC filter (SHIFT,

SCALE

and

BIG_SCALE),

the

coarse

gain

setting

(COARSE), the sum of the CFIR coefficients (CFIR_SUM),

the sum of the PFIR coefficients (PFIR_SUM), the fine gain

(FINE_GAIN), the sum of the resampler coefficients

(RES_SUM), the number of delays in the resampler filter

(NDELAY) and the final shift (FINAL_SHIFT). The overall

gain is shown below. The term in braces should be less than

or equal to unity. Note that the NDELAY term is unity if the

resampler is bypassed (see Section 3.5.6).

Unity gain is defined relative to the MSB of the I/O data.

Unity gain means that a maximum DC input with a tuning

frequency of zero, will produce a maximum DC output,

independent of the I/O words sizes.

3.7

PEAK COUNTER

Each channel has a peak counter which can monitor the

input signal’s strength, or can count the number of overflows

detected at three points within the channel. The peak counter

can count overflows due to the COARSE_GAIN circuit, it can

count overflows at the output from the CFIR, and it can count

overflows at the output of the PFIR.

If PEAK_MODE is set to 0 in address 28 of the channel

control page, then the peak counter will monitor the signal

strength at the input to the channel. The magnitude of each

input sample is compared against a threshold selected by the

PEAK_THRESH control in the same address. The threshold

can be 1/4, 1/2 3/4 or full scale. The peak counter increments

each time the magnitude equals or exceeds the threshold.

The input threshold crossings can be used in an AGC loop to

optimize the input signal level to the ADC.

If PEAK_MODE is 1, then the peak counter monitors

overflows at points selected by the PEAK_SELECT control in

address 26 of the channel control page. The peak counter

increments each time an overflow is detected. Note that the

data value is saturated to plus or minus full scale, as

appropriate, when the overflow occurs. The overflow count

can be used to check if the signal gain is set too high

anywhere along the processing chain.

The counter counts up to 255 and stops. The counter

value is saved in a holding register and the counter is cleared

by the sync selected by the PEAK_SYNC signal (see register

28). The sync can either be one of the chip’s input syncs, a

one-shot pulse, or the terminal count of the chip’s sync

counter. A periodic sync allows the user to count threshold

crossings or overflows during fixed time periods.

The user reads the count through the PEAK_COUNT

control register at address 29 of the channel control page.

The holding register contents are transferred to the

PEAK_COUNT register a clock cycle after the user reads the

PEAK_COUNT register. This transfer is delayed to prevent

the user from reading a peak count value at the same time

the circuit is updating the register.

Note that there are two other points in the chip where

overflows can occur. The first is at the input to the resampler

where samples from two channels can be added together as

when processing complex input data. This may cause an

overflow even though the samples feeding the resampler did

not overflow. If an overflow occurs here, the sample is

saturated and a control bit in the status register (address 1)

RES_GAIN

RES_SUM

32768

NDELAY

-----------------------------------------------

(

) 2FINAL_SHIFT

(

)

GAIN

NZEROS

---------------------

(

SHIFT

SCALE6

BIG_SCALE

–

(

)













COARSE

(

) CFIR_SUM

65536

-------------------

(

) PFIR_SUM

65536

-------------------

(

) FINE_GAIN

1024

--------------------

(

)

RES_SUM

32768

NDELAY

----------------------------------------------

(

) 2FINAL_SHIFT

(

)

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