GC4016 datasheet(17/83 Pages) TI

17 / 83 page

- 12 -

August 27, 2001

GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

This document contains information which may be changed at any time without notice

Table 2: Multichannel mode settings

Input

Real

Complex

Output

Rate

Two 2X output channels

Single 4x output channel

Output

Format

Complex

Real

Complex

Real

Complex

Real

Complex

Real

Channel

SPLITIQ

PHASE

-90 0

-90

QDLY_CFIR 0

IDLY_PFIR

QDLY_PFIR 0

NEG_CTL

IONLY

QONLY

ADD_TO

CHAN_MAP 0

3.5

RESAMPLER

The resampler will independently filter and change the

data rate of each channel. The most common application of

the resampler is to increase the sample rate of the data so

that it will match a desired symbol or bit rate. Demodulators

for digital modulation schemes, such as GMSK, QPSK, QAM

or CDMA, for example, require sample rates which are 1X,

2X, 4X or 8X times the bit or symbol rate of the modulation.

In these cases, the maximum down converter filter

performance is achieved when the PFIR output rate is

around 1.5 to 2 times the signal’s bandwidth1. The resampler

is then used to increase the sample rate up to the required

2X, 4X or 8X rate.

Section 7.7 shows example resampler configurations

and their performance.

The resampler can also be used as an additional filter to

optimize the passband or stopband response of the channel.

3.5.1 Functional Description

The

resampler

consists

input

buffer,

interpolation filter, and a final shift block. A functional block

diagram of the resampler is shown in Figure 12.

The resampler’s sampling rate change is the ratio

NDELAY/NDEC where NDELAY and NDEC are the

interpolation and decimation factors shown in Figure 12. The

decimation amount NDEC is a mixed integer/fractional

number. When NDEC is an integer, then the exact sampling

instance is computed and there is no phase jitter. If NDEC is

fractional, then the desired sampling instance will not be one

of the possible NDELAY interpolated values. Instead the

nearest interpolated sample is used. This introduces a timing

error (jitter) of no more than 1/(2*NDELAY) times the input

sample period.

The input buffer accepts 24 bit data from the four input

channels, and adds them as necessary to form 1,2, or 4

resampler channels (see the ADD_TO control bits in address

21 of the resampler control page). The input buffer serves

both as a FIFO between the channels and the resampler,

and as a data delay line for the interpolation filter. The 64

complex word input buffer can be configured as four

segments of 16 complex words each to support 4 resampler

1. The PFIR’s 63 tap filter’s stopband, transition band and passband ripple

performance improves as its output rate decreases relative to the signal’s

bandwidth. The resampler’s performance, however, begins to decrease when

the PFIR output rate is below 1.5 times the signal’s bandwidth.

INPUT

BUFFER

NDELAY

NDEC

FINAL

ROUND

Interpolation Filter

Fractional

Decimation

Resampling Filter

QTAP Filter Coefs

Figure 12. Resampler Channel Block Diagram

SHIFT

AND

OUT

GC4016 Datasheet(PDF) 17 Page - Texas Instruments

GC4016 Datasheet(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Datasheet Download

Link URL