GC4016 datasheet(7/83 Pages) TI

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August 27, 2001

GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

This document contains information which may be changed at any time without notice

3.0

FUNCTIONAL DESCRIPTION

The GC4016 quad receiver chip contain four identical

down-conversion circuits. Each downconvert circuit accepts

a real sample rate up to 100 MHz, down converts a selected

carrier frequency to zero, decimates the signal rate by a

programmable factor ranging from 32 to 16,384 and then

resamples the channel to adjust the sample rate up or down

by an arbitrary factor. In the real output mode the output

sample rate is doubled and the signal is output as a real

signal centered at Fout/4. The channels may be combined to

produce wider band and/or oversampled outputs or to

process

complex

input

data.

The

chip

outputs

the

down-converted signals in any one of several formats

(microprocessor, four serial lines, one TDM serial line,

nibble, LINK, or 24 bit parallel port. The chip contains two

user programmable output filters per path which can be used

to arbitrarily shape the received data’s spectrum. These

filters can be used as Nyquist receive filters for digital data

transmission. The chip also contains a resampling filter to

provide additional filtering and to allow the user complete

flexibility in the selection of input and output sample rates.

Two downconverter paths can be merged to be used as

a single complex input down-conversion circuit. Two paths

may also be combined to support wider band output rates or

oversampled outputs. Four paths may be combined to

support both wider band output and oversampling.

The downconverters are designed to maintain over 115

dB of spur free dynamic range and over 100 dB of out of band

rejection. A five stage CIC and 20 bit internal datapaths

support

this

high

dynamic

range

signal

processing

requirement. Each downconvert circuit accepts 16 bit inputs

and produces 24 bit outputs (can be rounded back to 12, 16,

or 20 bits). The frequencies and phase offsets of the four

sine/cosine sequence generators can be independently

specified, as can the decimation and filter parameters of

each circuit.

On chip diagnostic circuits are provided to simplify

system debug and maintenance.

The chip receives configuration and control information

over a microprocessor compatible bus consisting of an 8 bit

data I/O port, a 5 bit address port, a chip enable strobe, a

read strobe and a write strobe. The chip’s control registers (8

bits each) are memory mapped into the 5 bit address space

of the control port.

Sections 7.9 through 7.12 describe how to use the chip

for GSM, D-AMPS, CDMA and UMTS applications, including

control register values and filter coefficients.

3.1

CONTROL INTERFACE

The chip is configured by writing control information into

control registers within the chip. The control registers are

grouped into 8 global registers and 128 pages of registers,

each page containing up to 16 registers. The global registers

are accessed as addresses 0 through 7. Address 2 is the

page register which selects which page is accessed by

addresses 16 through 31. The contents of these control

registers and how to use them are described in Section 5.

The registers are written to or read from using the

C[0:7], A[0:4], CE, RD and WR pins. Each control register

has been assigned a unique address within the chip. This

interface is designed to allow the GC4016 chip to appear to

an external processor as a memory mapped peripheral (the

pin RD is equivalent to a memory chip’s OE pin).

An external processor (a microprocessor, computer, or

DSP chip) can write into a register by setting A[0:4] to the

desired register address, selecting the chip using the CE pin,

setting C[0:7] to the desired value and then pulsing WR low.

The data will be written into the selected register when both

WR and CE are low and will be held when either signal goes

high. An alternate “edge write” mode can be used to strobe

the data into the selected register when either WR or CE

goes high. This is useful for processors that do not guarantee

valid data when the write strobe goes low, but guarantee that

the data will be stable before the write strobe goes high. The

edge write mode is necessary for these processors, as some

control registers (such as most sync or reset registers) are

sensitive to transient values on the C[0:7] data bus.

To read from a control register the processor must set

A[0:4] to the desired address, select the chip with the CE pin,

and then set RD low. The chip will then drive C[0:7] with the

contents of the selected register. After the processor has

read the value from C[0:7] it should set RD and CE high. The

C[0:7] pins are turned off (high impedance) whenever CE or

RD are high or when WR is low. The chip will only drive these

pins when both CE and RD are low and WR is high.

One can also ground the RD pin and use the WR pin as

a read/write direction control and use the CE pin as a control

I/O strobe. Figure 2 shows timing diagrams illustrating both

I/O modes.

The edge write mode, enabled by the EDGE_WRITE

control bit in register 0, allows for rising edge write cycles. In

this mode the C[0:7] data only needs to be stable for a setup

time before the rising edge of the write strobe, and held for a

small hold time afterwards. This mode is appropriate for

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